Edward Au’s Post

CS standards webinar on 31 October: How to Create Better Analog IC Tests The quality of a test is best quantified by measuring the quality of ICs that pass the test, usually measured as defective parts per million (DPPM) after a device has been manufactured.  However, there is significant value in analyzing test quality before high-volume production to maximize test coverage while minimizing pattern count, something that digital ICs have done via fault modeling and simulation for many years.  With its upcoming publication, P2427, the IEEE Draft Standard for Analog Defect Modeling and Coverage, from IEEE Computer Society Test Technology Standards Committee, brings transparency to how test coverage can be calculated and communicated for analog and mixed-signal (AMS) intellectual property (IP) blocks, chiplets, and ICs. This IEEE Standards Association | IEEE SAs standard is expected to facilitate improving IC quality while reducing test-related costs. In this IEEE Computer Society monthly standards webinar, Steve Sunter, jeff rearick, Vladimir Zivkovic, and Anthony Coyette will first address motivating questions, such as: why is test time per transistor much larger for analog than it is for digital circuits, why is there so little automation for analog design-for-test (DFT) and test generation, and how can a circuit’s test coverage be measured objectively before manufacturing the circuit? Some essential terms will be defined, such as defect, fault, defect universe, and defect coverage, along with what should be included in a defect coverage summary. Then, several hypothetical industrial examples will be described where this standard can simplify, clarify, quantify, and speed the delivery and description of AMS circuit and test quality. You may visit the following link for complimentary registration: https://lnkd.in/egb_RMUn #ieee #ieeecs #ieeesa #standards #analog #integratedcircults #test Ian McIntosh

How to Create Better Analog IC Tests

How to Create Better Analog IC Tests

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