Kangguo Cheng

Semiconductor Industry Association Outlines Industry Recommendations for the National Semiconductor Technology Center 🇺🇸💡 SIA released a set of recommendations to promote the success of the National Semiconductor Technology Center (NSTC), a critical public-private research consortium established by the CHIPS and Science Act. SIA’s recommendations synthesize the most up-to-date industry consensus and priorities. The CHIPS & Science Act included the most significant federal investment ever made in chip research and development (R&D), committing a substantial $13 billion across the Departments of Commerce and Defense. The cornerstone of the CHIPS R&D program is the NSTC, a more than $5 billion initiative tasked to “conduct research and prototyping of advanced semiconductor technology and grow the domestic semiconductor workforce to strengthen the economic competitiveness and security of the domestic supply chain” (15 U.S.C. § 4656(c)(1). Since passage of the CHIPS Act, leading stakeholders have issued several valuable reports detailing recommendations and priorities for the initiation and operation of the NSTC. This body of work represents an emerging industry consensus that should form the guiding basis for the CHIPS R&D Office (CRDO) and Natcast—the new, purpose-built, non-profit entity created to operate the NSTC Consortium—in the establishment and operation of the NSTC. A big thank you again to Semiconductor Industry Association for the full article with more background and insights including the full report as FREE PDF Download via the link below 💡🙏👇 https://lnkd.in/e5aBA-K8 #semiconductorindustry #semiconductors #semiconductor #technology #tech #it #chips #innovation #chip #geopolitics #subsidies #usa #talent

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Maximize wafer yield at probe

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Here are some of the early results from one of the first ASML High NA EUV (High Numerical-Aperture Extreme Ultraviolet) machines in the world that was installed in the Albany Nanotech Complex and operated along with IBM. It uses lasers with a wavelength of 13.5nm to achieve high-resolution patterning down to 13nm (26nm pitch). Intel has these High NA EUV and TSMC is ordering them as well. #EUV #ASML #IBM #semiconductors #lithography #silicon #intel #TSMC #foundry Jordy Beuving Frederick Chen Marco Mezger Salah Nasri Marcelo Zuffo https://lnkd.in/gASMdq9P

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#Intel #20ANode #ArrowLake #Semiconductors #ChipManufacturing #TechIndustry #18ANode #Foundry #TSMC #Samsung #ProcessTechnology #RibbonFET #PowerVia #MooresLaw #ChipProduction Intel has decided to abandon the 20A node for production, particularly for its upcoming Arrow Lake processors. Here are the key reasons and implications of this decision: 1. Shift to external manufacturing: Intel will now rely on external foundries, likely TSMC, to produce all Arrow Lake components instead of using its own 20A node[1][3]. Intel's role will be limited to final packaging of the externally manufactured chiplets[3]. 2. Focus on 18A node: Intel is redirecting resources from 20A to the more advanced 18A node[1][2]. The company claims that 18A is progressing well, with a defect density below 0.40, indicating production readiness[1][3]. 3. Cost savings: By skipping the productization of the 20A node, Intel projects to save about $500 million in capital expenditures[1][4]. This aligns with the company's recent cost-cutting measures and restructuring efforts[4]. 4. Timeline and technological progression: The 20A node was originally intended to kick off Intel's "Angstrom era" and introduce key technologies like RibbonFET transistors and PowerVia backside power delivery[1][2]. However, Intel now plans to incorporate these advancements directly into the 18A node. 5. Learning and development: Despite not being used for production, the 20A node served as a crucial testbed for new techniques, materials, and transistor architectures. The learnings from 20A have contributed to the development of 18A[3]. 6. Strategic realignment: This decision allows Intel to optimize its engineering investments and potentially accelerate the deployment of its most advanced node (18A)[2][4]. It also aligns with Intel's focus on its foundry services, as evidenced by contracts with Microsoft and the U.S. Department of Defense for 18A production[4]. 7. Financial and operational challenges: The decision comes in the context of Intel's recent financial difficulties, including significant revenue declines and workforce reductions[4]. There have also been reports of manufacturing challenges, such as wafers failing tests conducted by Broadcom[4]. In summary, Intel abandoned the 20A node for production to streamline its technological progression, focus resources on the more advanced 18A node, and optimize costs in the face of financial and operational challenges. While this represents a departure from their original plans, Intel sees it as a strategic move to maintain competitiveness in advanced chip manufacturing. https://lnkd.in/g_UHJHV2

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Recently, there has been a lot of discussion about TSMC's advanced packaging . Let us provide an in-depth introduction to the packaging of this foundry giant through their financial reports and the latest technology summit . Information shows that after Zhang Zhongmou returned to the company in 2011, he made up his mind to do advanced packaging . Yu Zhenhua, who joined the company in 1994, is the leader of this "secret" project of TSMC. CoWoS technology is TSMC's small test in this field. Their technology was first implemented on Xilinx FPGAs , and the InFO packaging derived from this has shined on Apple processors, and has since made TSMC's packaging famous all over the world. Popular science on TSMC’s advanced packaging technology According to Semiwiki, last year, TSMC merged their 2.5D and 3D packaging products into a single, comprehensive brand 3DFabric. Among them, 2.5D packaging technology CoWoS can be divided into CoWoS and InFO series. First look at CoWoS technology, which can be divided into the following types: 1. CoWoS -S Chip-on- wafer - on -substrate with silicon interposer for die-to-die redistribution layer (RDL) connections is celebrating its big break 10th year of series manufacturing. 2. CoWoS -R The CoWoS -R option replaces the (expensive) silicon interposer spanning the 2.5D die placement area with an organic substrate interposer. The trade-off with CoWoS-R is the smaller line spacing of the RDL interconnects—for example, 4 micron spacing on organic compared to the submicron spacing of CoWoS-S. 3. CoWoS -L Between Silicon -S and Organic-R interposer options, the TSMC CoWoS family includes a newer product with a “native” silicon bridge for (ultra-short distance) interconnect between adjacent die edges. These silicon wafers are embedded in an organic substrate and provide high-density USR connections (with tight L/S spacing) as well as interconnect and power distribution capabilities to (thick) wires and planes on the organic substrate. Note that CoWoS is designated as a "chip last" assembly process, with the chip attached to a fabricated interposer. Maximum package size and RDL enhancement CoWoS -S: 3X reticle (certified in 2021); CoWoS -R: 45X mask (3X in 2022), 4 RDL layers on organic substrate (W/S: 2um/2um), using SoC + 2 HBM 2 die stack for reliability certification; CoWoS -L: 1.5X reticle size reliability evaluation test tool with 4 local interconnect bridges between 1 SoC and 4 HBM 2 chip stacks; InFO _oS: 5X reticle (51mm x 42mm on 110mm x 110mm package ), 5 RDL layers (W/S: 2um/2um), currently under reliability evaluation; #business #india #china #europe #buy #globalbusiness #headhunter #usa #automotive #automotiveindustry #leadership #motivation #kindness #bestadvice #personaldevelopment #linkedin #hiring #careers #help #employment #happiness #jobs #health #global #world #jobchange #process #plasma #Knlowledgestudy #buyer #globalbusiness #Technology #recycle

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We are pleased to introduce TSMC 3DFabric™, our comprehensive family of 3D Silicon Stacking and Advanced Packaging Technologies. 3DFabric complements our advanced semiconductor technologies to unleash our customer's innovations. Packaging technologies were once considered just backend processes, almost an inconvenience. Times have changed. Computing workloads have evolved more over the past decade than perhaps the previous four decades. Cloud computing, big data analytics, artificial intelligence (AI), neural network training, AI inferencing, mobile computing on advanced smartphones and even self-driving cars are all pushing the computing envelope. #business #india #china #europe #buy #globalbusiness #headhunter #usa #automotive #automotiveindustry #leadership #motivation #kindness #bestadvice #personaldevelopment #linkedin #hiring #careers #help #employment #happiness #jobs #health #global #world #jobchange #process #plasma #Knlowledgestudy #buyer #globalbusiness #Technology #recycle

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TSMC's 3D Stacked SoIC Packaging Making Quick Progress, Eyeing Ultra-Dense 3μm Pitch In 2027 TSMC's 3D-stacked system-on-integrated chips (SoIC) advanced packaging technologies is set to evolve rapidly. In a presentation at the company's recent technology symposium, #TSMC outlined a roadmap that will take the #technology from a current bump pitch of 9μm all the way down to a 3μm pitch by 2027, stacking together combinations of A16 and N2 dies. #TSMC has a number of #advancedpackaging technologies, including 2.5D #CoWoS and 2.5D/3D InFO. Perhaps the most intriguing (and complex) method is their 3D-stacked system-on-integrated chips (SoIC) technology, which is TSMC's implementation of hybrid #wafer bonding. #Hybridbonding allows two advanced logic devices to be stacked directly on top of each other, allowing for ultra-dense (and ultra-short) connections between the two chips, and is primarily aimed at high performance parts. For now, SoIC-X (bumpless) is used for select applications, such as AMD's 3D V-cache technology for #CPUs, as well as their Instinct MI300-series #AI products. And while adoption is growing, the current generation of the technology is constrained by limitations on die sizes and interconnection pitches. Thanks again to Anton Shilov and AnandTech for the full article with more background and insights via the link below 🙏💡👇 https://lnkd.in/ePCq3din #semiconductorindustry #semiconductors #semiconductor #technology #tech #it #chip #chips #ic #innovation #taiwan #foundry #nvidivia #hbm

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Good overview of semiconductor value chain by Quartr, folks who are not that familar with the semiconductor industry might find this useful.

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#TSMCNanoFlex #Semiconductor #ChipDesign #ProcessNode #AdvancedTechnology #N2 #Nanosheet #DTCO #PerformanceOptimization #AIChips TSMC's NanoFlex is an innovative technology designed to enhance the capabilities of their upcoming 2nm (N2) process node. This breakthrough in design-technology co-optimization offers significant flexibility and performance improvements for chip designers. https://lnkd.in/g797Z5pz ## Key Features of NanoFlex **Flexible Cell Design** NanoFlex allows chip designers to mix and match standard cells from different libraries within the same block design. This flexibility enables the creation of: - Short cells: Emphasizing small area and greater power efficiency - Tall cells: Maximizing performance **Design Flexibility** NanoFlex allows for flexibility in chip design with the use of different cell heights within the same design. This means designers can mix and match:Standard cells (8T) High-performance cells (10T) Ultra-high-performance cells (12T) **Performance Improvements** - Up to 15% higher performance in tailored designs - 12% boost in energy efficiency over the base 2nm process **Compatibility with GAA Nanosheet Transistors** NanoFlex works in conjunction with TSMC's gate-all-around (GAA) nanosheet transistors used in the N2 process family. This combination allows for even greater control over transistor characteristics, as GAA nanosheet transistors enable adjustments to channel width for optimized performance or power efficiency. ## Applications and Benefits 1. **Customization**: Designers can create chips that combine multiple transistor types with different power-efficiency, speed, and size configurations. 2. **Optimization**: The technology enables fine-tuning of chip designs to optimize performance or power consumption based on specific project requirements. 3. **Versatility**: NanoFlex provides the ability to address various application needs within a single chip design, from high-performance computing to low-power mobile devices. 4. **Improved Efficiency**: By allowing for more precise control over transistor characteristics and cell design, NanoFlex contributes to overall improvements in chip efficiency and performance. ## Availability and Future Prospects NanoFlex will be available with TSMC's N2 process node, which is should enter risk production in 2025 and high-volume manufacturing in the second half of 2025. https://lnkd.in/gMmgxJQ5 As TSMC continues to advance its process technologies, NanoFlex represents a significant step forward in enabling more flexible and efficient chip designs, particularly for applications requiring a balance of high performance and power efficiency, such as artificial intelligence and mobile computing.

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Enabling 2.5D/3D Multi-Die Package Both approaches to integrating multiple #chiplets have unique challenges 💡 In the rapidly evolving world of #ASIC design, the shift from monolithic to 2.5D and 3D multi-die architectures represents a significant leap forward. This approach, which integrates multiple chiplets (also knowns as dies) into a single package, demands not only a new level of #IC design #innovation but also an increased complexity in coordination and integration. At the forefront of this technological revolution is Global Unichip Corp. (GUC), which has effectively harnessed the power of Synopsys Inc’ 3DIC Compiler, a unified exploration-to-signoff platform, to streamline its #chip design processes and reduce overall cycle time. GUC recently presented their multi-die tape-outs at SNUG Silicon Valley 2024, which were made more efficient by Synopsys’ 3DIC Compiler through the implementation of die floorplanning and related bump assignments. 3DIC Compiler helped further check the physical and logical connectivity, sync up information from die to die quickly, and, ultimately, shorten chip design cycle timelines for GUC’s 2.5 and 3D #CoWoS designs. This distinction between 2.5D and 3D IC design approaches becomes critical in addressing the increasing demand for higher performance and more integrated systems. Each method comes with its unique set of challenges and benefits, tailored to specific application needs. Thanks again to Kenneth Larsen and Semiconductor Engineering for the full article with more background and insights via the link below 💡🙏👇 https://lnkd.in/e48EXEFw #semiconductorindustry #semiconductor #foundry #advancedpackaging #technology #icdesign #usa #chip #tech #semiconductormanufacturing

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Micron Technology Reportedly Set to Build New #DRAM Plant in #Hiroshima, #Japan, Operational Expected by End of 2027 💡 According to a report from a Japanese media outlet The Daily Industrial News, it reported that #Micron Technology plans to build a new plant in Hiroshima Prefecture, Japan, for the production of DRAM #chips, aiming to begin operations as early as the end of 2027. The report estimates the total investment to be between JPY 600 billion and 800 billion (roughly USD 5.1 billion). Construction of the new plant is scheduled to begin in early 2026, with the installation of extreme ultraviolet (#EUV) #lithography equipment. The Japanese government has approved subsidies of up to JPY 192 billion (roughly USD 1.3 billion) to support Micron’s production of next-generation chips at its Hiroshima plant. The Ministry of Economy, Trade and Industry stated last year that this funding would help Micron incorporate ASML’s EUV equipment, with these chips being crucial for powering #generativeAI, #datacenters, and #autonomousdriving #technology. Thanks again to TrendForce Corporation for the full article with more background and insights via the link below 💡🙏👇 https://lnkd.in/e5-AW75n #semiconductorindustry #semiconductors #semiconductor #technology #it #tech #semiconductormanufacturing #innovation #geopolitics #ic #ai #computing

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My article on Semiconductor Packaging  .. please write in comments what more you would like to read about semiconductor packaging  https://lnkd.in/giXs5DJX

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A very nicely explained article on how Semiconductor Packaging is done. I sincerely thank Mr. Bhairav Shah ji for writing this article as a part of one of the activities of Semiconductor Ecosystem Development Group (SEDG), which is reaching to more and more people day by day. #semiconductors #packaging #ATMP #OSAT #indiansemiconductormission

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https://lnkd.in/ethDyF98 Anis Rahman Chief Technology Officer, President Applied Research & Photonics, Inc. Harrisburg, PA, United States Silicon carbide (SiC) is an important semiconductor for high temperature and high voltage applications such as in electric vehicles. The SiC boule is grown by seeded sublimation deposition process where the primary ingredients viz. carbon (C) and silicon (Si) are sublimated at very high temperature. Eddy and Gaskill [1] indicated that the variations in the atomic ratio of Si to C in the vapor phase that arise from feedstock granularity is difficult to minimize during growth. It is also difficult to avoid impurities arising from both in the SiC feedstock and in the graphite-insulation used in the growth reactor. Additionally, radial, and axial thermal profiles in the reactor and boule may cause polycrystallinity, grain boundary formation, and other defects in the lattice, which may lead to macro- and micro-domain formation. Because the understanding of materials’ properties at the extreme growth temperature of ~2200°C is incomplete, the boule growth modeling efforts are based on extrapolated parameters. Thus, an accurate experimental quantification is very important. The evolution of domain walls in single crystalline SiC is therefore very difficult to eliminate, and they stay put in the boule. This paper investigates SiC substrates and epitaxial SiC wafers via cameraless T-ray imaging route. T-ray images reveal significant features that were not seen before. “Dendrimer dipole excitation (DDE)” T-ray source was used that generates wider terahertz bandwidth (0.1 THz to ~30 THz) and generate >200 milliwatts of CW power without requiring a femto-second pulsed laser. An instrument system, the T-ray nanoscanning and 3D imager (TN3DI), has been designed around the DDE T-ray source that was used for the present investigations. Here the wafer was directly mounted on the nanoscanner and the whole wafer was scanned for imaging. T-ray images (see Fig. 1) have revealed some patterns in the SiC wafers of the present investigation that were unseen previously. Optical images and T-ray images were compared side-by-side that shows that the T-ray exhibits higher sensitivity and clearer images thus reveals internal intricate pattern not visible by the optical and X-ray technique. Here, we propose that the unique patterns observed from the T-ray images are due to some kind of domain formation in the boule that has remained in the wafers even after slicing and polishing. This hypothesis is further strengthened via T-ray micrograph of different wafers that exhibit many micro-domains on the epi layer of a 100 mm SiC wafer. Thus, the T-ray images have revealed some intricate patterns for the first time that are present in the SiC wafers. Details of the principle and experimental will be presented.

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