Andrew Kensler

Can Gowin beat Xilinx and Altera in the educational market? Gowin Semiconductor is at the Sensors Converge exhibition in Santa Clara today. I went to their booth yesterday and met the team: CEO Jason Zhu, sales, marketing and application engineers. We discussed the topic of the educational boards used for EE classes, such as 6.111 at the Massachusetts Institute of Technology (MIT). Every ASIC designer working at Samsung, Apple, NVidia and similar companies has taken a similar class back in school. It is not possible to train an RTL designer using a Verilog simulator only. In order to develop intuition in static timing analysis (STA) and how many resources are inferred for a given RTL code, a student has to either use FPGA or ASIC synthesis, and with FPGA, he also gets the benefit of working with an actual design. This fact makes educational FPGA boards a critical technology for any country’s high-tech workforce development, a topic that now concerns even the US Government, as I heard at the Design Automation Conference in San Francisco a day earlier. Gowin has an opportunity to grab this market from Xilinx and Altera. For two reasons: 1) price and 2) synthesis speed. Synthesis in Gowin IDE runs an order of magnitude faster than on Xilinx Vivado. A design of a graphical game with sprites is synthesized in 209 seconds with Xilinx Vivado and just 22 seconds with Gowin. Altera is in the middle: 56 seconds. If you are a student working on a project, this is a big deal, since you run synthesis with every code change, and if you do this 20 times a day, waiting minutes instead of seconds is annoying, and Gowin IDE speed gives a totally different user experience. Now let’s discuss what do we need for an educational FPGA board - https://lnkd.in/gpxUCnrr

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In this Doulos KnowHow tip, Doulos certified instructor Brian Jensen reviews the usage of static and automatic variables in System Verilog, before simulating an example in EDA Playground. https://lnkd.in/eGVdmXpM #DoulosOnDemand #SystemVerilog #CommonMistakesInSystemVerilog

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HEYO أولاً الحمدلله 😃 VERY proud of this, albeit being a simple project, I'm very glad to say that I've finished re-implementing the verification of a simple memory using UVM. I realize this is seemingly abit too simple but in reality I've gained so much knowledge from applying what I learnet from both cruising siemens' verification academy forums and diligently studying and applying Ray Salemi's "Adaptable coding vs Interactable coding" from "The UVM Primer". so I'm just gonna list the stuff I learnet, aside from the obvious: 1. Adaptability (was my main goal and focus) 2. Realizing the treasure that uvm_factory actually is (whoever had the idea to bring that into existence is just a MAGNIFICENT being) 3. Config classes 4. UVM Sequence Arbitration 5. Difference between m_sequencer & p_sequencer 6. how to use post_body & pre_body tasks and alternatives to them 7. debugging uvm_config_db/uvm_resource_db (which was just hell btw🤣) using +UVM_CONFIG_DB_TRACE as well as usual debugging techniques 8. Reporting using the reporting utilities provided by the UVM 9. Tracking/Debugging TLM ports using get_provided_to and get_connected_to 10. Scoreboard debugging 11. `uvm_do macros, although I have yet to use them 12. Hours of back-tracking functions and tasks through the uvm library just for curiosity and sometimes debugging There's some stuff that I still wanna add and will add every now and then. You can find it on: https://lnkd.in/dGUc4g8s Currently delving deeper with the help of the UVM cookbook: https://lnkd.in/dqh5CyC7 while implementing the Verification of a Synchronous FIFO, as well as exploring cocotb's docs! : https://lnkd.in/d-NpddyS

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Keeping your data close to the GPUs is essential, so we offer VAST Data as part of our #GPUasaService AI Platform. Let us help you #StepontheGaaS and move your #AI strategy forward. #Fast #Secure #Private Dominic Ken Michael Bill Traci

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📣 From algorithms to atoms, NVIDIA ALCHEMI NIM microservice catalyzes sustainable materials research for EV batteries, solar panels, and more. This is accelerating the discovery of novel materials to expedite the renewable energy transition. #SC24 Read the blog ➡️ https://nvda.ws/4hQOMtR

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In our latest episode of IDZ news, we explain how you can deploy and manage high-performance LLMs at scale using OpenVINO Model Server. Check out the full episode to find out how you can access software components over standard network protocols and gain efficient resource utilization: https://intel.ly/3C5DKk2 #OpenVINO #Networking #Software

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🔬 New research from @UTSWMedCenter creates a 4D deep learning #AI model for identifying #breastcancer metastasis using only MRI and clinical data, for early detection without invasive biopsies.🩺 🔗 Learn more: https://nvda.ws/3YppB8V #BreastCancerAwarenessMonth

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Stop the data copy cycle. When a processor receives data over a 10-gigabit connection, it can spend many cycles simply copying that data. Learn how offloading this type of task to Intel DSA 2.0 on #IntelXeon 6 processors increases throughput and reduces latency. https://intel.ly/47plzkI #TechnologyLeadership #DigitalTransformations

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"Get Ready for On-Device AI! Intel's Lunar Lake Powers Up Copilot+ PCs" At Computex 2024, Intel showcased its next-generation processors codenamed "Lunar Lake." These chips prioritize artificial intelligence (AI) performance with a dedicated neural processing unit (NPU) boasting up to 48 trillion operations per second (TOPs). This NPU offers advantages in both cost and power efficiency, according to Intel. Lunar Lake processors are designed to be compact. This allows for slimmer laptops with potentially larger batteries and slightly reduced production costs. Memory-wise, these processors can support up to 32 GB of RAM, with even basic models offering at least 16 GB – double the RAM found in Apple Silicon-powered MacBooks. In terms of total AI performance, Lunar Lake reaches up to 120 TOPs. This breaks down to 5 TOPs from the CPU, 48 TOPs from the NPU, and 67 TOPs from the Xe2 graphics processing unit (GPU). This NPU edges out Qualcomm's Snapdragon X Elite and X Plus, which offer 45 TOPs of AI performance.📈 Lunar Lake processors are expected to be the driving force behind Intel-based Copilot+ PCs launching later this year, competing directly with ARM-based Copilot+ PCs. Additionally, Intel unveiled a developer kit featuring a Lunar Lake processor that can be upgraded to future generations. Lunar Lake represents a significant leap for Intel, potentially becoming their flagship product. These processors boast several first-of-their-kind features for Intel chips. The first wave of Lunar Lake laptops is anticipated to hit shelves globally by the end of 2024, with some offering on-device generative AI capabilities. What do you think? Could Lunar Lake be a game-changer for AI-powered laptops? Let us know your thoughts in the comments below! #intel #computex #AIpoweredLaptops #LunarLake #copilotPCs

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AMD Reveals Adaptive SoCs With RF Conversion and 80 TOPS DSP https://vist.ly/3mpimpv

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Dive into how KV cache early reuse, fine-grained blocks, and efficient eviction algorithms can supercharge TTFT speeds. Efficient KV cache use is key to improving #LLM model response, speeding up #inference, and maximizing throughput. With NVIDIA TensorRT-LLM's advanced KV cache management features, developers can take inference performance to the next level. ➡️ https://nvda.ws/3YJzpe4

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Generating KV cache during #inference requires a lot of compute and memory resources, so efficient use is key to improving model response, accelerating inference, and increasing system throughput. TensorRT-LLM provides advanced reuse features to further optimize TTFT response times for peak performance. Start using TensorRT-LLM KV cache reuse with the documentation on GitHub ➡ https://lnkd.in/gHeHRcyr Technical blog: ➡ https://lnkd.in/gP6WcFtN

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📣Join Texas Instruments and MathWorks on December 11 to learn about Model-Based Design using #MATLAB and #Simulink to generate code for Texas Instruments #C2000 real-time #microcontrollers. Jayakarthigeyan Prabakar from MathWorks and Chen-Yu Chang from Texas Instruments will demonstrate the benefits of a model-based design approach to developing C2000 applications using a HEV/EV HVAC eCompressor motor control design example. The topics covered will be: • TI’s C2000 MCU Portfolio • Walkthrough of HEV/EV HVAC eCompressor motor control reference design • Model-based design for Embedded Software Development using Automatic code generation • MathWorks C2000 Microcontroller Blockset • Model-based reference design example for eCompressor motor control running on C2000 MCU December 11 at 9:00 a.m. CST Registration link: https://spr.ly/6040QPO3q

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