Process Integration/Device Engineer
Greater Minneapolis-St. Paul Area
Process Integration/Device Engineer
Greater Minneapolis-St. Paul Area
Self-motivated team-working semiconductor process and device professional with more than 11 years of experience in major semiconductor companies and a hard disk/solid state drive manufacturer
• Device physics, CMOS device engineering, and process integration
• Device test and characterization, reliability and root-cause failure analysis
• New test structures and characterization methodologies development
• Evaluation of electrical/physical property in identifying main failure modes
• Statistical data mining with six-sigma methodology (Green-belt)
• Analytical device modeling and FEM based TCAD simulation
• Semiconductor and hard disk knowledge
(Public Company; STX; Computer Hardware industry)
February 2008 — July 2009 (1 year 6 months)
• STRAM/RRAM cell devices development, and technology integration
(Public Company; MU; Semiconductors industry)
October 2004 — February 2008 (3 years 5 months)
• Process integration to develop CMOS and cell transistors (68 to 54nm)
• Test structures design and qualification method establishment
• Device measurement, parametric analysis, and numerical modeling
(Public Company; Electrical/Electronic Manufacturing industry)
September 1997 — September 2004 (7 years 1 month)
• Built and led 7 members of team developing advanced MOS-Tr
• Common mode failures analysis, potential Q&R risk identification
• Gate oxynitride processes, C-V/I-V characterization, TDDB, and EM
(Research industry)
September 1995 — September 1997 (2 years 1 month)
Ph.D./M.S. , Materials Science and Engineering/Physics , 1986 — 1998
• Si(001)-SiO2 interface, MEIS spectroscopy, SIMOX SOI
• Wide band gap semiconductors (DLC and group-III nitrides), ECR-CVD
• YBCO high Tc superconducting thin film, MOCVD
Senior Member, IEEE
Marquis Who's Who in the World, 2010