Richard Price

Richard Price

Senior Engineering Manager, FPGA Central at Altera

Location
San Francisco Bay Area
Industry
Semiconductors

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Richard Price's Overview

Current
  • Senior Engineering Manager, FPGA Central at Altera
Past
  • Senior Engineering Manager, IC Design at Altera
  • Senior Engineering Manager, HardCopy Design Center at Altera
  • Senior IP Design Engineer at Altera
  • Senior ASIC Design Engineer at Altera
  • VLSI Design Engineer, DSP Group at GEC Plessey Semiconductors
  • IC Design Engineer, Communication BU at GEC Plessey Semiconductors
  • NCG Design Engineer, Radio Products Group at Plessey Company plc
Education
Connections

500+ connections

Richard Price's Experience

Senior Engineering Manager, FPGA Central

Altera

Public Company; 1001-5000 employees; ALTR; Semiconductors industry

March 2013Present (1 year 7 months) San Francisco Bay Area

Managed a small highly proficient full chip timing team to architect, develop and deploy robust static timing verification methodology for Altera's programmable logic fabric. In this highly cross functional role, I engage with many technical teams (Software Engineering, Hard and Soft IP Development, Product Development, Product Engineering and Design Automation) across the organization on activities such as full chip timing verification, flow development and automation, timing model verification, QuartusII FPGA design software QA and model correlation to silicon. Another aspect of my role is to influence the future direction of timing models and timing analysis methodologies across these organizations, for example: evaluate new EDA tools to solve the complexities of programmable logic & routing fabric timing modelling. My team is also responsible for full chip clock verification as well as influencing the clock architecture of the next generation product family to enable ease of integration and verification.

Senior Engineering Manager, IC Design

Altera

Public Company; 1001-5000 employees; ALTR; Semiconductors industry

January 2009March 2013 (4 years 3 months) San Francisco Bay Area

Managed place and route team for Altera's 28nm Stratix V & Cyclone V FPGA families. Drove multiple methodology-firsts for FPGA design, including embedded metal-programmable HardCopy blocks; ASIC versus full-custom routing channel implementation for Cyclone V; ASIC rather than full-custom implementation of 28nm & 20nm transceiver testchips with right-first-time success. These methodology improvements resulted in multi-$M savings due to die-size reduction and schedule acceleration. Also managed silicon interposer development for a 2.5D product integrating multiple die into a single assembly. Recognised as a technical leader by participation on the judging panel in Altera’s annual Technical Symposium. Represented IC Design in cross functional Device Spec Change committee.

Senior Engineering Manager, HardCopy Design Center

Altera

Public Company; 1001-5000 employees; ALTR; Semiconductors industry

July 2000January 2009 (8 years 7 months) San Francisco Bay Area

Built from scratch, a team of 25 engineering staff distributed across two ASIC Design Centers in San Jose, California and Penang, Malaysia. Responsible for over 200 Hardcopy ASIC tapeouts spanning 40nm, 90nm, 130nm & 180nm technology nodes, generating in excess of $600M in revenue for the company. Was recognized by Department VP for 'above & beyond' technical support for key HardCopy customer engagements. As a brand new product line for Altera I worked in a startup-mode to contribute both technical development and business development activities to this product. Specifically:

Product development: Built formal verification flows, STA flows for first generation device. Wrote SDC constraints and developed DDR memory interface timing analysis methodology. Hands-on backend ASIC physical implementation, timing, logical & physical closure through post silicon technical support, and silicon prototype approval.

Business development: Performed competitive analysis Presented new product to over 200 engineers at the Worldwide FAE conference in San Francisco. Pre and post sales customer visits to Japan, China, Europe & US. Mentored and developed engineers and first level managers under my charge.

Operational: Managed multiple complex customer design projects simultaneously, requiring sound timely technical decisions making and engineering judgment calls. Built ITAR certified design center & infrastructure. Managed budget for compute & EDA infrastructure. Led both on-site & remote silicon debug. Wrote datasheet for first generation HardCopy device family. Facilitated outsourcing due to peak customer demand. Performed customer design reviews.

Senior IP Design Engineer

Altera

Public Company; 1001-5000 employees; ALTR; Semiconductors industry

February 2000July 2000 (6 months) San Francisco Bay Area

Developed, from scratch one of Altera’s DSP IP cores. The “NCO Compiler” v1.0 written by me in Verilog and Java, allowed the user to generate several different architectures at the click of a button. It produced synthesizable verilog code, as well as Matlab models, Simulink and Verilog testbenches. Wrote RTL source code obfuscation tool in perl enabling delivery to customers of protected simulatable verilog models for Verilog XL, NC Verilog, VCS & Modelsim logic simulators.

Senior ASIC Design Engineer

Altera

Public Company; 1001-5000 employees; ALTR; Semiconductors industry

May 1997February 2000 (2 years 10 months) San Francisco Bay Area

Developed highly automated design flow for retargeting Altera FPGA designs into ASIC. Taped out several chips with this flow on technologies up to and including 0.25 um. Implemented 4 * Flex 10K100 FPGAs into a single ASIC. Netlist was handed off to Silicon vendor (TSMC) for physical implementation. Wrote entire synthesis, test fixing, scan insertion and static timing analysis scripts in tcl. Performed flow regression testing & enhancement. Used the following tools: dc_shell, VCS, pt_shell, Tetramax, Max Plus II, QuartusII. As the engineering lead of this team, I was the primary technical interface with the silicon vendor, EDA tool vendors, and IP suppliers. Also performed wire bond, and flip chip package design, floorplanning, gate count, die area estimation, and power estimation.

VLSI Design Engineer, DSP Group

GEC Plessey Semiconductors

September 1995May 1997 (1 year 9 months) Swindon, United Kingdom

Supported the integration of a third party DSP processor core into large ASIC designs. Successfully integrated the DSP core into a 0.6um chip for use in a GSM cellphone. Synthesized the RTL to gates with Synopsys Design Compiler. Ran transistor level static timing analysis using Pathmill on the critical path of the DSP core to assess performance on next generation technology nodes (0.5um, 0.35um). Ran transient simulations in Cadence Spectre on a post layout extracted view of the core. Generated the Synopsys Liberty timing model of the block, in addition to a Verilog timing model for gate level timing simulation.

IC Design Engineer, Communication BU

GEC Plessey Semiconductors

December 1990September 1995 (4 years 10 months) Swindon, United Kingdom

Worked on a mixed signal 0.8um CMOS IC that formed part of a chip set for an analog cellular telephone. Ran mixed-signal simulations in Verilog-Spectre, of a fractional-N frequency synthesizer. Designed some high frequency custom digital circuitry as well as a reduced voltage swing analog output stage. Introduced high degree of automation for this project by authoring many useful UNIX shell scripts. Evaluated the first silicon and characterized several functional blocks on it using a variety of laboratory equipment. Designed a digital filter and implemented partial scan circuitry on an ultra low power 1.4um digital paging decoder chip. Performed spice simulations to check PLA functionality at 1V.

NCG Design Engineer, Radio Products Group

Plessey Company plc

Public Company; 10,001+ employees; Plessey; Telecommunications industry

December 1989December 1990 (1 year 1 month) Swindon, United Kingdom

Performed lab evaluation of the breadboard of a GSM frequency synthesizer. Acquired system level knowledge of the GSM protocol. Learned lots about phase locked loops and frequency synthesis. Spent six months on a graduate training program visiting other disciplines within the business: eg: IC Design, Wafer Fab, Test Eng, Product Eng, Packaging, Burn In and QA.

Richard Price's Projects

  • Altera Makers

    • September 2013 to Present
    Team Members: Richard Price

    I started a company-wide grassroots initiative called “Altera Makers” to showcase Altera’s FPGAs at the 2014 Bay Area Maker Faire ( http://makerfaire.com/ ). Currently, there are over 100 employees spanning all Altera sites involved in this activity.
    Press coverage:
    http://www.marketwatch.com/story/altera-programmable-logic-inspires-innovation-at-2014-maker-faire-bay-area-2014-05-14
    http://www.eetimes.com/document.asp?doc_id=1322401&print=yes

Richard Price's Skills & Expertise

  1. Semiconductors
  2. ASIC
  3. FPGA
  4. Verilog
  5. Logic Synthesis
  6. Timing Closure
  7. Static Timing Analysis
  8. TCL
  9. EDA
  10. Altera
  11. Analog
  12. Technical Leadership
  13. Design Compiler
  14. Technical Presentations
  15. DFT
  16. Formal Verification
  17. Primetime
  18. P&R
  19. PLL
  20. Perl
  21. DRC
  22. LVS
  23. ITAR
  24. MS Project
  25. Silicon debug
  26. Physical Design
  27. RTL design
  28. IC
  29. VLSI
  30. Functional Verification
  31. Low-power Design
  32. Floorplanning
  33. Digital Signal Processors
  34. Debugging
  35. Integrated Circuit Design
  36. ModelSim

View All (36) Skills View Fewer Skills

Richard Price's Patents

  • Using a single mask for various design configurations

    • United States Patent 8796740
    • Issued August 5, 2014

    Techniques and design methologies for using a single mask set to create devices of different sizes are disclosed. A maks with a plurality of tiles is disclosed. Each of the tiles has a number of fixed resource blocks, multiple logic blocks and is surrounded by a scribe region. The tiles may be connected to one or more adjacent tiles through interconnect lines that enable the fixed resource and logic blocks in one tile to communicate with the fixed resource and logic blocks in an adjacent tile. The mask set may be used to produce devices of different sizes. Using a mask set that can handle a variety of design sizes with varying resources may in turn reduce mask cost.

  • Method for programming a mask-programmable logic device and device so programmed

    • United States Patent 7,290,237
    Inventors: Richard Price, Steven Perry, Gregor Nixon, Larry Kong, Alastair Scott, Andrew Hall, Lingli Wang, Chris Dettmar, Jonathan Park

    A user logic design for a mask-programmable logic device ("MPLD") may be designed on a comparable or compatible user-programmable logic device ("UPLD") and migrated to the MPLD, or may be designed directly on an MPLD. If the design is designed on a UPLD, the constraints of the target MPLD--i.e., differences between the devices--are taken into account so that the migration will be successful. If the design is designed directly on an MPLD, constraints of a comparable compatible UPLD are taken into account if the user indicates that the design will be migrated to the UPLD for testing. This means that when a logic design is intended to be migrated back-and-forth between a UPLD and an MPLD, only the intersection of features can be used. To facilitate migration, fixed mappings between pairs of devices may be created.

  • Method and apparatus for tesing memory embedded in a mask-programmable logic device

    • United States Patent 6,680,871
    Inventors: Richard Price

    In a mask-programmable logic device having embedded memory blocks, which device cannot be reconfigured for testing like a full programmable logic device, the embedded memory blocks are tested by forming scan chains from the input-side registers of a plurality of embedded memory blocks, and from the output-side registers of a those embedded memory blocks. Test vectors are clocked into the input-side scan chain and the results are clocked out from the output-side scan chain. The test vectors can be made by concatenating multiple copies of a test vector for one block when the blocks are identical. The method works even where one or more embedded memory blocks are configured as read-only devices, as long as the contents of the read-only devices are known so that one knows what test output to expect.

Richard Price's Education

Bangor University

BSc Hons, Microelectronics & computer engineering

19851989

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