CTO and VP Engineering at Parimics, Inc.
San Francisco Bay Area
CTO and VP Engineering at Parimics, Inc.
San Francisco Bay Area
Founder and member of the executive management team in a Silicon Valley startup who is highly methodical, analytical and results-oriented. Proven skills in architecting, designing, implementing and evangelizing new paradigms in the areas of networks and network processors, on- and off-chip interconnects, low-latency switching, and supercomputers as well as processors for image analysis. Previous successes include the turnaround of a company that was considered a $36M loss to investors into a $394M acquisition target, by convincing the Technical Advisory Board and the Board of Directors to strategically reorient the company, then by architecting, implementing and marketing a new paradigm. My experience ranges from high-level system hardware and software co-design to ASIC architecture definition and design to the creation and implementation of special-purpose processors. Proven track record in protecting intellectual property by writing enforcible methods and implementation patents. Involved in standardization organizations to make sure that viable and implementable technology and processes are defined. Verifiable success in advising companies through active participation in their Technical Advisory Board. Technology evaluation expert and member of patent review committees. Sharing my knowledge and experience by writing books and articles, white papers, and teaching the CTO classes - institutionalizing the inventive process - in the framework of the Silicon Valley Executive Business Program at UCSC as one of three facilitators.
Basic research in physics and information technology and the intersection thereof. Vast experience in high-performance computing (HPC, aka supercomputing) and in low-latency interconnects. Processors for data communication and for hard real-time image analysis purposes. General-purpose supercomputers, clusters and grids. Turning a new paradigm into a workable and sellable solution. Authoring books and enforcible patents.
(Privately Held; 11-50 employees; Semiconductors industry)
October 2002 — Present (6 years 10 months)
CTO and VP of Engineering, Founder, Visionary, Inventor, Implementer. Evangelizing a new paradigm one more time...
(Higher Education industry)
January 2004 — October 2008 (4 years 10 months)
One of three CTO Class Facilitators in the Silicon Valley Executive Business Program ("mini-MBA") at UCSC. This class is not held in 2008, but we'll hopefully resume in 2009!
(Privately Held; 11-50 employees; Semiconductors industry)
June 2000 — October 2002 (2 years 5 months)
Member of the TAB and Principal System Architect. Reoriented the company towards a communications switch fabric, away from the ccNUMA SMP-type crosspoint switch. Turned a loss to investors into a gain. Stayed on board after acquisition by Conexant and spinoff into Mindspeed. During that period retained to be TAB member at Z-Force, now Attune Systems.
(Public Company; 10,001 or more employees; IFX; Semiconductors industry)
April 1998 — June 2000 (2 years 3 months)
PhD , Physics & Informatics , 1985 — 1991
Institutionalizing the inventive process, change management, management theories derived from Peter Drucker's ground-breaking work, corporate ethics, long-term corporate vision versus short-sighted quarterly focus. Being a CTO and teaching what it takes to be one.
IEEE, Torrenza initiative, IBTA, NPF