Alfred Crouch

Current

• Chief Technologist & Director of IJTAG R&D at ASSET-InterTech

Past

• Chief Scientist and Director of DFT R&D at Verigy
• Chief Scientist and Director of DFT R&D at Inovys Corporation
• Design-for-Test Manager at Motorola

• Design-for-Test Engineer at Digital Equipment Corp.
• Design-for-Test Engineer at Texas Instruments

see less...

2 more...

Education

• University of Kentucky
• University of Kentucky

Recommended

3 people have recommended Alfred

Connections

249 connections

Industry

Semiconductors

Alfred Crouch’s Summary

Author of best-selling Industry Text "Design for Test for Digital ICs and Embedded-Core Systems"

Author of more than 30 papers and publications in the field of DFT and Test Automation and Inventor on more than 15 issued patents in the field of Test and Design-for-Test.

Vice-Chair and driver of the IEEE Working Group team that developed the 1687 IJTAG Hardware Architecture Specification for embedded instruments and connectivity options; and member of the team that is creating the normative rules for the architecture.

Currently investigating developing products based on the concepts of the IEEE P1687 IJTAG proposed standard as well as IEEE 1500 and IEEE 1149.7.

Senior Member of the IEEE.

Alfred Crouch’s Experience

• Chief Technologist & Director of IJTAG R&D

  ASSET-InterTech

  (Privately Held; 51-200 employees; Electrical/Electronic Manufacturing industry)

  March 2008 — Present (1 year 9 months)

  As Chief Technologist and Director of IJTAG R&D of the Core Instrument Division in the Austin Office it is my goal to work with customers and partners to develop new products and directions based on the concepts based around the IEEE P1687 IJTAG proposed standard (of which I am the Vice-Chair of the IEEE Working Group). This involves creating tools and methodologies based on using the 1149.1 Test Access Port or an Embedded CPU to access, control, configure, operate, and collect data from embedded instruments inside of semiconductors. These embedded instruments are commonly DFT, DFD, and DFY type of logics such as [DFT] Memory BISTs, Logic BISTs, Scan-Compression, Core Test Wrappers, Clock-Controllers; [DFD] Embedded Logic Analyzers, Trace Buffers, Bus and Traffic Monitors; [DFY] Process Monitors, Voltage Monitors, Temperature Sensors -- and normal functional logic such as Bus Configuration or Power Configuration.

• Chief Scientist and Director of DFT R&D

  Verigy

  (Public Company; 1001-5000 employees; VRGY; Semiconductors industry)

  January 2008 — March 2008 (3 months)

  Verigy acquired Inovys and my position changed to more of a Strategic Marketing Assessment instead of Technology Exploration and Development.

• Chief Scientist and Director of DFT R&D

  Inovys Corporation

  (Privately Held; 11-50 employees; Semiconductors industry)

  October 2001 — December 2007 (6 years 3 months)

  As Chief Scientist, Director of R&D in the Austin Verigy DFx Technology Center, and the Director of EDA Partnerships, it was my job to work with customers and partners to develop new links and uses between structural testers and design-side tools such as ATPG, STA, Layout, and Debug and Diagnosis. In addition, to push the bounds of the structural tester with DFT techniques that enabled it to be used to characterize timing, power, thermal limits, and functional operation using AC Scan, BIST, and loadboard micro-instrumentation. And to have developed yield and failure-analysis solutions based on structural test techniques and data collection.

• Design-for-Test Manager

  Motorola

  (Public Company; 10,001 or more employees; Semiconductors industry)

  January 1992 — October 2001 (9 years 10 months)

  In my last position, I developed DFT methodologies and managed a DFT team involved with DFT architecture development and vector generation for various microprocessor chips and cores -- such as the 68k/ColdFire.

• Design-for-Test Engineer

  Digital Equipment Corp.

  (Public Company; Semiconductors industry)

  1990 — 1992 (2 years )

• Design-for-Test Engineer

  Texas Instruments

  (Public Company; Semiconductors industry)

  1987 — 1990 (3 years )

Alfred Crouch’s Education

• University of Kentucky

  MSEE , Electrical Engineering: Quantum Electronics , June 1986 — August 1987

  Activities and Societies:

  Tau Beta Pi, Eta Kappa Nu

• University of Kentucky

  BSEE , Electrical Engineering , January 1981 — May 1985

  Graduated with Distinction

  Activities and Societies:

  Tau Beta Pi, Eta Kappa Nu, VA Representative