Adam Selsley

Substrate Engineer at Crystal IS

Location
Albany, New York Area
Industry
Semiconductors

As a LinkedIn member, you'll join 300 million other professionals who are sharing connections, ideas, and opportunities.

  • See who you and Adam Selsley know in common
  • Get introduced to Adam Selsley
  • Contact Adam Selsley directly

View Adam's full profile

Adam Selsley's Overview

Current
  • Process Engineer-Substrate Fabrication at Crystal IS
Past
Education
Connections

500+ connections

Adam Selsley's Summary

Semiconductor process engineer with expertise in CVD and PVD thin film deposition. I have worked with numerous films including, TEOS, BPSG, Silicon Nitride, TiN, Ti, Al, W, WSix,Ta, TaN, and Cu. I also have expertise in the relevant metrology techniques to measure these films.

Specialties: Back-end metallization specialist/ ISO9000/TS16949 systems and auditing

Adam Selsley's Experience

Process Engineer-Substrate Fabrication

Crystal IS

Privately Held; 11-50 employees; Semiconductors industry

July 2014Present (3 months) Green Island, NY

Member Technical Staff Process Engineer

GLOBALFOUNDRIES

Privately Held; 10,001+ employees; Semiconductors industry

April 2011July 2014 (3 years 4 months) Malta, NY

April 2011-October 2013: Back end of the line process development engineer focusing is on TiN metal hard mask, MIMcap, TSV barrier/seed, and terminal (aluminum) metal.

November 2013-present: Project manager on the Convergence Team. Part of the team overseeing the creation of a strategic plan to converge processes from different technologies to maximize current asset usage.

Also served as Internal ISO 9000 auditor helping to ensure the integrity of our quality management systems.

Lean Six Sigma Greenbelt Candidate

Sr. Process Engineer

TEL Technology Center, America

Public Company; 10,001+ employees; Semiconductors industry

January 2007March 2011 (4 years 3 months)

A sampling of my achievements and responsibilities since joining TEL Technology Center, America as a Senior Process Engineer in the copper barrier/seed area are:

• Developed low damage barriers for 22nm and beyond ULK interlayer dielectrics
• Lead a collaborative meeting between barrier/seed process development and integration to enhance advanced barrier seed development
• Tool owner for development barrier/seed platform and related metrology
• Managed relationships with multiple external customers in collaborative developments
• Developed barrier/seed process that resulted in the complete filling of very high aspect ratio through silicon vias

Electronic Engineer

Intel Corporation

Public Company; 10,001+ employees; INTC; Semiconductors industry

March 2006January 2007 (11 months)

At Intel, as the thin film module engineer in the Substrate Technology Research Line I accomplished:

• Took over leadership of the sputter working group for the Fine Line and Space Program
• Developed a solution to substrate low resistance issues that were slowing the progress of the Fine Line and Space Program
• Mentored others in the STRL in statistics and Design of Experiments
• Supported the thin film needs of other programs as necessary

Program Manager

Fairchild Semiconductor

Public Company; 5001-10,000 employees; FCS; Semiconductors industry

September 2004March 2006 (1 year 7 months)

In the role of Product Line Program Manager for the Low Power Discrete Group, I:

• Managed new product development projects whose resources included a diverse group of engineers located across the United States, as well as in the Far East
• Ensured that projects meet the internal quality requirements and are completed on time, in budget, and within scope
• Worked independently to set daily and weekly goals and objectives in support of projects being managed
• Developed excellent communication and interpersonal skills in order to work with people with diverse cultural backgrounds

Sr. Process Development Engineer

Fairchild Semiconductor

Public Company; 5001-10,000 employees; FCS; Semiconductors industry

May 1999September 2004 (5 years 5 months)

As a Senior Process Development Engineer, my responsibilities and past accomplishments include, but are not limited to:

• Process development and sustaining on the AMAT P5000, Novellus M2i and Concept 2, and Semitool vertical furnaces
• Developed a manufacturable low deposition rate PECVD TEOS that utilized the current equipment configuration instead of requiring extensive tool modifications
• Developed and qualified an HDP oxide deposition processes for both a MEMS and a CMOS/BiCMOS process flow that utilized the same hardware to maximize manufacturability of both processes
• Worked with process integration to determine what films are needed to fulfill device requirements

Process Engineer

Micron Technology

Public Company; 10,001+ employees; MU; Semiconductors industry

April 1995April 1999 (4 years 1 month)

At Micron, I progressed from a pilot line CVD sustaining engineer to CVD development engineer. During this time I:

• Worked on process development and sustaining on the AMAT P5000, Centura, Endura, and Watkins-Johnson WJ1000
• Developed advanced contact metallization schemes
• Implemented Brookside software as a diagnostic tool and trained other engineers to use it properly
• Optimized processes through Design of Experiments

Process Engineer

Toshiba Display Devices

June 1994March 1995 (10 months)

As a Process Engineer at Toshiba Display Devices my responsibilities included:

• Process sustaining of the Panel-Mask Assembly Area
• Defect reduction projects
• ISO 9000 Documentation

Adam Selsley's Patents

  • Methods of forming inter-poly dielectric (IPD) layers in power semiconductor devices

    • United States Patent 8,143,123
    • Issued March 27, 2012
    Inventors: Adam Selsley, Steven Sapp, Gary Dolny, Peter Wilson, Barmak Sani, Christopher Kocon
  • Method of forming conductive connections

    • United States Patent 6,316,353
    • Issued November 21, 2001
    Inventors: Adam Selsley

    A method of forming a conductive connection between a first region and a second region includes forming a first titanium comprising layer over and in electrical connection with the first region. The first layer is exposed to a nitrogen containing plasma effective to transform at least an outer portion thereof into a second layer comprising titanium nitride. An elemental titanium comprising third layer is formed over the second layer. The third layer is exposed to a nitrogen containing plasma effective to transform at least an outer portion thereof into a layer comprising titanium nitride. The second region is formed over and in electrical connection with the transformed third layer. A method of forming a conductive line includes a conductively doped silicon comprising semiconductive material being formed. Titanium is deposited over the semiconductive material to form a first layer in electrical connection with the semiconductive material. The first layer is exposed to a nitrogen containing plasma effective to transform at least an outer portion thereof into a second layer comprising titanium nitride. Titanium is deposited to form an elemental titanium comprising third layer over the second layer. The third layer is exposed to a nitrogen containing plasma effective to transform at least an outer portion thereof into a layer comprising titanium nitride. A metal is deposited in electrical connection with the transformed third layer. The semiconductive first layer, second layer, third layer, transformed third layer and metal materials are formed into a conductive line

  • Method of forming a conductive contact

    • United States Patent 6,649,518
    • Issued September 24, 2001
    Inventors: Adam Selsley

    An opening is formed within insulative material to proximate a silicon comprising substrate. Titanium is deposited within the opening to form a first layer comprising titanium suicide. It is exposed to a nitrogen containing plasma effective to transform at least an outer portion thereof into a second layer comprising titanium nitride. Titanium is deposited within the opening to form an elemental titanium comprising third layer. The third layer is exposed to a nitrogen containing plasma effective to transform at least an outer portion thereof into a layer comprising titanium nitride. A metal is deposited within the opening over the transformed third layer. Any remnant of first layer, second layer, third layer, transformed third layer and metal materials is removed from over the insulative material to form an isolated conductive contact within the opening. At least the depositing to form the first layer is by chemical vapor deposition.

  • Sequential tantalum-nitride deposition

    • United States Patent 7,642,201
    • Issued January 24, 2008

    An iPVD system is programmed to deposit uniform material, such as barrier material, into high aspect ratio nano-size features on semiconductor substrates using a multi-step process within a vacuum chamber which enhances the sidewall coverage compared to the field and bottom coverage(s) while minimizing or eliminating overhang.

  • Hybrid in-situ dry cleaning of oxidized surface layers

    • United States Patent 8,227,344
    • Issued February 26, 2010

    According to one embodiment, the method includes providing a substrate containing a metal-containing barrier layer having an oxidized surface layer, exposing the oxidized surface layer to a flow of a first process gas containing plasma-excited argon gas to activate the oxidized surface layer and applying substrate bias power during the exposing of the oxidized surface layer to the flow of the first process gas. The method further includes exposing the activated oxidized surface layer to a second process gas containing non-plasma-excited hydrogen gas, wherein the exposure to the first process gas, in addition to activating the oxidized surface layer, facilitates chemical reduction of the activated oxidized surface layer by the second process gas containing the hydrogen gas. A thickness of the metal-containing barrier layer is not substantially changed by the hybrid in-situ dry cleaning process.

Adam Selsley's Volunteer Experience & Causes

  • Volunteer Experience

    • Assistant Scoutmaster

      Troop 33
      • Children

Adam Selsley's Skills & Expertise

  1. Design of Experiments
  2. Thin Films
  3. Semiconductors
  4. SPC
  5. R&D
  6. Electronics
  7. Engineering Management
  8. Lean Manufacturing
  9. Manufacturing
  10. Process Engineering
  11. Engineering
  12. Continuous Improvement
  13. Program Management
  14. Product Development
  15. Cross-functional Team Leadership
  16. Root Cause Analysis
  17. FMEA
  18. CVD
  19. Semiconductor Process
  20. PVD
  21. Process Integration
  22. Materials Science
  23. PECVD
  24. Silicon
  25. Metrology
  26. Process Simulation
  27. Sputtering
  28. MEMS
  29. Semiconductor Industry
  30. JMP
  31. CMOS
  32. Design for Manufacturing
  33. Product Engineering
  34. Yield
  35. IC
  36. Etching
  37. Plasma Etch
  38. Failure Analysis
  39. Characterization
  40. Atomic Layer Deposition
  41. Microelectronics
  42. Device Characterization
  43. Photolithography
  44. Semiconductor Fabrication

View All (44) Skills View Fewer Skills

Adam Selsley's Education

Penn State University

MBA, Business Administration and Management, General

20042006

Rensselaer Polytechnic Institute

MS, Materials Engineering

19921995

Activities and Societies: Pep Band, RPI-Sage Hillel, Phi Sigma Kappa, Rensselaer Space Society, Materials Research Society Student Chapter

Rensselaer Polytechnic Institute

BS, Materials Engineering

19871991

Activities and Societies: Pep Band, RPI-Sage Hillel, Phi Sigma Kappa, Rensselaer Space Society, Materials Research Society Student Chapter

Contact Adam for:

  • career opportunities
  • job inquiries
  • expertise requests
  • reference requests
  • getting back in touch

View Adam Selsley’s full profile to...

  • See who you and Adam Selsley know in common
  • Get introduced to Adam Selsley
  • Contact Adam Selsley directly

View Adam's full profile

Viewers of this profile also viewed...