Staff R&D Engineer (IC design and Physical Implementation)

Synopsys - Mountain View, CA

Posted 504 days ago
  • Experience
    Mid-Senior level
  • Job function
    Engineering
  • Employment type
    Full-time
  • Industry
    Computer Software
  • Job ID
    5033594

This is a preview of the Staff R&D Engineer (IC design and Physical Implementation) job at Synopsys. To view the full job listing, join LinkedIn - its free!Join LinkedIn - its free!

About this job

Job description

Job Description and Requirements

Seeking a highly motivated individual with expertise in IC design and physical implementation. Responsibilities include floorplanning and partitioning, timing constraints, physical synthesis, clock tree generation, routing, extraction, timing closure, DFT, signal integrity, physical verification and DFM. The individual will contribute both on the implementation side as well as flow development for a variety of mixed signal IP products and test-chips at 32nm and below. This requires close interaction and collaborative team work with multiple functional groups (front end, analog, application).

The candidate may be involved in technical steering, driving and reporting of remote group’s activity.


The successful candidate:
- has solid engineering understanding of the underlying concepts of IC design
- has intimate knowledge of the full design cycle from RTL to GDSII
- is an expert with the physical implementation flows and methodologies in deep sub-micron designs

- has experience in high performance digital design and CAD, high-speed design, low-power design, high speed clock design and distribution.

- has experience in timing closure, signal integrity.

- has good software and scripting skills (Perl, Tcl, Python, ..) ; knowledge of CAD automation methods.  
- Contributes to enhancing the best practices of the physical design flow
- Can interface with the larger product team to understand design constraints, deliverable formats, customer requirements

- has good communication skills, ability to think and communicate at different levels of abstraction

 

Desired Skills and Experience

BS with 10+ years experience or MS with 8+ years experience. Must have hands-on experience with physical design of complex ASSP and COT designs. Must also demonstrate knowledge of the Synopsys tools, flows and methodologies required to execute physical design projects. These tools may include: Design Compiler, Physical Compiler, Primetime SI, ICC, Star-RCXT, Hercules, ICV, HSPICE and other tools. Will have proven experience contributing to project tape-outs. Will have demonstrated experience as a technical contributor on physical design projects and as project lead.

About this company

Synopsys

Company Description: Synopsys is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, IP and services used in semiconductor design and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and FPGA solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has more than 60 offices located throughout North America, Europe, Japan, Asia and India

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