Yves Deweerdt

Current

• Consultant at De Valck Consultants

Past

• Design Engineer at Easics
• Application/Sales Engineer at Barco Communication Systems

Education

• Universiteit Gent

Recommended

3 people have recommended Yves

Connections

168 connections

Industry

Semiconductors

Yves Deweerdt’s Summary

Hardware development engineer specialized in Front-End ASIC and FPGA design.

Yves Deweerdt’s Specialties:

VHDL, Xilinx, Altera, Actel
C/C++

Yves Deweerdt’s Experience

• Consultant

  De Valck Consultants

  (Semiconductors industry)

  September 2004 — Present (5 years 4 months)

• Design Engineer

  Easics

  (Public Company; 11-50 employees; Semiconductors industry)

  September 2001 — August 2004 (3 years )

• Application/Sales Engineer

  Barco Communication Systems

  (Public Company; 501-1000 employees; Broadcast Media industry)

  August 2000 — August 2001 (1 year 1 month)

Yves Deweerdt’s Education

• Universiteit Gent

  M. Sc. Burgerlijk Ingenieur , Computer Science , 1995 — 2000

  Dissertation title: Extraction of a high resolution still image out of an image sequence.

  Activities and Societies:

  Werkgroep Computerwetenschappen

Additional Information

Yves Deweerdt’s Groups:

•    ASIC & FPGA Engineers: www.ASICForum.com
•    ASIC CONSULTANTS NETWORK
•    FPGA - Field Programmable Gate Array
•    Alumni Universiteit Gent
•    FPGA/CPLD Design Group
•    K VIV - Koninklijke Vlaamse Ingenieursvereniging
•    ASIC and FPGA Professionals
•    ASIC Design & Verification
•    ASIC Design
•    ASIC/VLSI Design
•    Semiconductor - VLSI
•    ASIC (Application Specific Integrated Circuit) Community
•    ASIC Methodology Experts Network

Yves Deweerdt’s Contact Settings

Interested In:

• consulting offers
• new ventures
• job inquiries
• expertise requests
• business deals
• reference requests
• getting back in touch