Yves Deweerdt

Consultant at De Valck Consultants

Antwerp Area, Belgium

Current
Past
Education
  • Universiteit Gent
Connections
168 connections
Industry
Semiconductors

Yves Deweerdt’s Summary

Hardware development engineer specialized in Front-End ASIC and FPGA design.

Yves Deweerdt’s Specialties:

VHDL, Xilinx, Altera, Actel
C/C++


Yves Deweerdt’s Experience

  • Consultant

    De Valck Consultants

    (Semiconductors industry)

    September 2004Present (5 years 4 months)

  • Design Engineer

    Easics

    (Public Company; 11-50 employees; Semiconductors industry)

    September 2001August 2004 (3 years )

  • Application/Sales Engineer

    Barco Communication Systems

    (Public Company; 501-1000 employees; Broadcast Media industry)

    August 2000August 2001 (1 year 1 month)


Yves Deweerdt’s Education

  • Universiteit Gent

    M. Sc. Burgerlijk Ingenieur , Computer Science , 19952000

    Dissertation title: Extraction of a high resolution still image out of an image sequence.

    Activities and Societies:
    Werkgroep Computerwetenschappen

Additional Information

Yves Deweerdt’s Groups:

  •    ASIC & FPGA Engineers: www.ASICForum.com
  •    ASIC CONSULTANTS NETWORK
  •    FPGA - Field Programmable Gate Array
  •    Alumni Universiteit Gent
  •    FPGA/CPLD Design Group
  •    K VIV - Koninklijke Vlaamse Ingenieursvereniging
  •    ASIC and FPGA Professionals
  •    ASIC Design & Verification
  •    ASIC Design
  •    ASIC/VLSI Design
  •    Semiconductor - VLSI
  •    ASIC (Application Specific Integrated Circuit) Community
  •    ASIC Methodology Experts Network

Yves Deweerdt’s Contact Settings

Interested In:

  • consulting offers
  • new ventures
  • job inquiries
  • expertise requests
  • business deals
  • reference requests
  • getting back in touch

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