
Staff Electrical Engineer / EDA Methodology Manager
Melbourne, Florida Area

Staff Electrical Engineer / EDA Methodology Manager
Melbourne, Florida Area
ASIC and FPGA designer with a strong background in ASIC and FPGA EDA tools. Provides strategic direction on ASIC and FPGA EDA tools. Manages, maintains, and supports Harris GCSD's ASIC/FPGA EDA design environment, serving 200 design engineers with EDA tools from Synopsys, Cadence, Mentor, Denali, Synplicity, Xilinx, Actel, Altera, Lattice, Honeywell. Provides tactical ASIC/FPGA tool support to Harris GCSD’s design community. Completed 8 FPGA designs and 4 ASIC designs.
ASIC/FPGA Design
Languages: VHDL, MCL, Perl, HTML
Design Tools: Nedit, vi, Mentor Visual Elite, EMA Timing Designer
FPGA tools: Synplify Pro, Synplify Premier, Xilinx, Altera, Actel, and Lattice
ASIC tools: Synopsys Design Compiler (Ultra), Synopsys Primetime, Synopsys Primepower, Synopsys Module Compiler, Honeywell
Verification tools: Cadence Affirma (NC Sim), Denali MMAV, Synopsys Formality, Synopsys DesignWare, Synopsys Leda
Computing Tools: Sun Grid Engine
Bird Watching, Home Theater, Macintosh, Cars, Audi, Technology, Science, Simpsons, Travel, Fine Food, Wine, Psychology