HV/PMIC and Package FTS Technical Manager at TSMC
Taiwan
- Current
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- HV/PMIC, Package FTS Technical Manager at TSMC
- Past
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- High Voltage Reliability Section Manager at TSMC
- SRAM Development Engineer at TSMC
- Process Integration Engineer at TSMC
- Thin-Film Engineer at Mosel/Vitelic
- Metallurgy Engineer at Yin King Industrail Corp.
- Marketing Intern at TNS Global
- Education
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- National Tsing Hua University
- Chung Yuan Christian University
- Recommended
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3 people have recommended Sunnys - Connections
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- Semiconductors
Sunnys Hsieh’s Summary
My goal is achieving finance independent and lifelong career, such as self-employ or consulter. With variety of interesting; music, marketing and product study (Especially on computer, consumer and communication product), you can referral my personal BLOG. If possible, I will try to join or develop my skill on these areas. Prefer by English communicate; Mandarin Chinese and Taiwanese or Simple Japanese is also accepted (Two months assignee in Japan).
Career Summary
2009/10~ HV/PMIC and Advanced Package Field Technical Service Division
2005/06~ High Voltage (HV) Reliability Section Manager, tsmc. Responsible for responding as the major key contact for all tsmc HV reliability related matters. Cross internal resource arrangement. Providing industrial formal safe operation area for HV analog designer in 3Q, 2007
2000/05~ SRAM Develop Engineer, tsmc Was Major design owner on 65nm and Key process RD owner on 0.13um SRAM; referring to publication ICMTS 2004. Till now still provide 40nm SRAM sanity (Vg bining) check for FAB production.
1995/09~ Thin Film Engineer and Process Integration Engineer, Mosel-Vitelic and tsmc
Were Focused on Metal Film, epically on tungsten and also responsible for Dielectric, referring to publication ISSM 2000 and Focused on BEOL Test-key design and DRAM process integration.
Also try to find some turn key solution transform from light to electrical signal and vice versa in the near future.
Sunnys Hsieh’s Specialties:
Coordination and commute with people across organization for whole IC business operation from tape out into chip final test between foundries, HV (High voltage ~ 200V) Device reliability and SRAM process sanity test key design. HV and UHV (Ultra HV) Parameter Tool develop and setup, current interested in UHV (1100V), High Current (10A) and Pulse Mode (100ns~1us~10ms). Next topic might be ESD (HBM/MM/CDM/FIM) or MEMS related study.
Sunnys Hsieh’s Experience
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HV/PMIC, Package FTS Technical Manager
TSMC
(Public Company; TSM; Semiconductors industry)
October 2009 — Present (2 months)
2009/10~ HV/PMIC and Advanced Package Field Technical Service Division
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High Voltage Reliability Section Manager
TSMC
(Public Company; 10,001 or more employees; TSM; Semiconductors industry)
June 2005 — October 2009 (4 years 5 months)
The key function is focus on high voltage device reliability. Voltage range from 5V to KV (500V, 700V and etc.); also demonstrate capability for setup 1st cost acceptable workable KV (1100V) WAT and reliability tester with Realtest and Keithley Taiwan. The HVMOS contains as following as BCD, LDMOS, DEMOS and field-gap DEMOS.
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SRAM Development Engineer
TSMC
(Public Company; 10,001 or more employees; TSM; Semiconductors industry)
April 2000 — June 2005 (5 years 3 months)
Worked on RD, job function is 65nm and 0.13um SRAM development. The majority job is setup the proto type on 65nm and developing a serial of 0.13um HS, LV, G, LP and ULP in branches and. Publication in the period: Optimization of 2.14 um2 6T-SRAM cell by using Cell-like Test Structures: ICMTS 2004. Mar 22-25, Awaji Yumebutai, Japan. Sunnys Hsieh, R.F. Tsui, Wesley Lin, C.Y. Yang, J.J. Liaw, Kelvin Y.Y. Doong and C.-M. M. Wu (TSMC Ltd., Taiwan R.O.C). Also be owner of setup and maintain tsmc RD TCAD server room for both hardware and software (Linux/Windows/HP).
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Process Integration Engineer
TSMC
(Public Company; 10,001 or more employees; TSM; Semiconductors industry)
September 1997 — April 2000 (2 years 8 months)
Focus on 0.25um BEOL test key design and 0.22um DRAM. Publication: "Optimization of Low-k Dielectric (Fluorinated SiO2) Process and Evaluation of Yield Impact by Using BEOL Test Structures", 2000 IEEE International Conference on Microelectronic Test Structures, March, 2000, Monterey, USA"
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Thin-Film Engineer
Mosel/Vitelic
(Semiconductors industry)
September 1995 — August 1997 (2 years )
Dedicate on Tungsten CVD, CVD-TiN and Sputter, also response scrubber, stripper process and film metrology and defect tools.
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Metallurgy Engineer
Yin King Industrail Corp.
(Machinery industry)
September 1995 — September 1995 (1 month)
Machine Parts Metallurgy
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Marketing Intern
TNS Global
(Market Research industry)
June 1989 — September 1989 (4 months)
Marketing Intern: Interviewer with target client for marketing information collection, majority focus on automotive owner and Electronic parts user (EMS or OEM/ODM)
Sunnys Hsieh’s Education
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National Tsing Hua University
Master , Chemical Engineering , 1993 — 1995
Working on Taxol extracting and Analysis by counter current chromatography and high performance liquid chromatography under Dr. I.M.Chu instruction.
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Chung Yuan Christian University
Bachelor , Chemistry , 1989 — 1993
Was intern in Inorganic Chemistry Laboratory of Dr. Andrew Yeh.
Additional Information
Sunnys Hsieh’s Interests:
Cycling and Swimming. Sometime also be jogging. Also like to variety of books.
Sunnys Hsieh’s Groups:
The Club of Promotion Cycling in HSINCHU science Industry Park., GPM, EXECUTIVE SEARCH, International Network of Social Entrepreneur
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Semiconductor Manufacturing
Sunnys Hsieh’s Honors:
Patent Award of TSMC 2002
18 papers and 16 patterns in semiconductors domain
Sunnys Hsieh’s Contact Settings
Interested In:
- career opportunities
- consulting offers
- new ventures
- job inquiries
- expertise requests
- business deals
- reference requests
- getting back in touch
