Agile Software Developer
Greater Los Angeles Area
Agile Software Developer
Greater Los Angeles Area
Results oriented, agile developer specialized in developing highly scalable and efficient software.
Excellent fluency in algorithms and data structures. Agility in XP and Scrum, Expert level C/C++ knowledge, rapid prototyping, Optimization of multiple objectives in the presence of multiple constraints.
(Public Company; XLNX; Semiconductors industry)
2008 — 2009 (1 year )
Congestion aware implementation tools enable the use of chips with fewer metal layers, providing both the customers and the company significant cost savings. As part of congestion reduction task force, I had been responsible for developing diagnostic tools that graphically examine the congestion profile of NCDs, instituting benchmarking for validating various proposed solutions and for innovating placer algorithm modifications to alleviate congestion.
Been part of second memory reduction task force and continued to reduce memory consumed by the placer system. After reducing the memory foot print of placer sub system significantly in the previous task force, there was not many opportunities for memory reduction. Despite that, I was able to contribute for about 4% peak memory reduction using more advanced and invasive methods.
Joined the global optimization group that develops specialized algorithms to provide bleeding edge performance to customers for various flows tailed to metrics such as fMax, area and power. Initial project focused on improving fMax of area flow and runtime and I delivered 4% better fMax and 8% runtime reduction without any area penalty. Later, I focused on improving fMax flow. For fMax flow, we delivered 6% better fMax (ISE 11.1) on synplicity netlists when compared to the default non-global_opt flow.
(Public Company; XLNX; Semiconductors industry)
2005 — 2007 (2 years )
Revamped placer data structures to improve memory by 42.6% for large designs (available since ISE 9.1/9.2). This accounted for a third of the total memory savings reported. http://www.xilinx.com/prs_rls/2007/software/0786_ise92i.htm
Improved global placement and detail placement algorithms by algorithm re-factoring and other tunings to get 2X speedup of these algorithms. Larger designs show greater percentage of improvement.The changes are memory neutral and QoR neutral on average. (available since ISE 10.1)
http://press.xilinx.com/phoenix.zhtml?c=212763&p=irol-newsArticle&ID=1121032&highlight=
(Educational Institution; Higher Education industry)
1999 — 2004 (5 years )
Research Assistant -- Data Mining, Multilevel Clustering, Hypergraph Partitioning, Multi-Objective and Multi-Constraint handling in hypergraph partitioning and partitioning driven placement.
Teaching Assistant -- Data Structures and Algorithms, Internet Programming and Computer Architecture.
(Privately Held; Semiconductors industry)
2002 — 2002 (less than a year)
Monterey Design Systems had a highly integrated backend implementation tool (integrating synthesis, placement and routing). The tool was a multi-threaded and used multi-level algorithm design for further speedup. I researched and invented some new clustering algorithms and metrics that reduced congestion by 32% on average.
Ph.D. , Computer Science , 1999 — 2004
The graduate school work had spanned data mining algorithms, graph partitioning algorithms and EDA algorithms. The thesis focused on developing scalable algorithmic solutions for some of the unique challenges faced by VLSI physical design automation.
BSc (Hons) , Computer Science , 1995 — 1999
Thesis focused on evolving fuzzy rules for ATM/SONET network controller using genetic algorithmic approach.