Ronald Goodstein

Current

• Consultant at First Shot Logic Simulation and Design (Sole Proprietorship)

Past

• Consultant at Goodrich Corporation
• Consultant at Freescale Semiconductor
• Electrical Engineer (Contractor) at Zaiq Corporation

• Electrical Engineer (Contractor) at Intel Corporation
• Electrical Engineer (Contractor) at ATI
• Electrical Engineer (Contractor) at Instrinsix
• Vice-chair at IEEE Consultants Network
• Electrical Engineer (Contractor) at Nortel Networks
• Electrical Engineer (Contractor) at stratus computer
• Electrical Engineer (Contractor) at BBN
• Consultant at Tellabs
• Electrical Engineer (Contractor) at chipcom corporation
• Electrical Engineer (Contractor) at IBM
• Electrical Engineer (Contractor) at NCR
• Electrical Engineer at Digital Equipment Corporation

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12 more...

Education

• Boston University
• Syracuse University

Recommended

3 people have recommended Ronald

Connections

457 connections

Industry

Computer Hardware

Websites

• My Website
• IEEE Consultants Network

Ronald Goodstein’s Summary

I am an electrical engineer with 20+ years experience
in designing and verifying SoC ASIC and FPGA devices. RTL Languages I use are VHDL, Verilog, C and C++. Also used DO-254

Ronald Goodstein’s Specialties:

Languages: C/C++, Verilog, VHDL, Verisity/E, PLI, VERA, SystemC, TCL
Simulators: Synopsys VCS, Cadence Verilog NC Sim, Modelsim
EDA Tools: Synopsys Design Compiler, Primetime, Synplicity, Leonardo Spectrum
O/S's: Unix, Linux, Sun O/S, AIX, Windows XP
Devices: Xilinx, Altera, Actel, Toshiba, TSMC, NEC
Protocols: ATM, 10/100/1000 Mb Ethernet, SCSI, PCI,SONET,AGP,OC192, AMBA
Revision Control: RCS, SCCS, CVS, Atria Clearcase

Ronald Goodstein’s Experience

• Consultant

  First Shot Logic Simulation and Design (Sole Proprietorship)

  (Sole Proprietorship; 1-10 employees; Computer Hardware industry)

  January 2002 — Present (6 years 5 months)

  Created bus functional model of PCI bus interface to multicore ASIC SoC that used 8 ARC processors using Verilog. Also participated in Boston and San Jose Synopsys Users Group on Technical committee.

• Consultant

  Goodrich Corporation

  (Public Company; 501-1000 employees; Aviation & Aerospace industry)

  August 2006 — July 2007 (1 year)

  Verified Actel APA1000 FPGA used on A380 Motorcontroller using VHDL, Modelsim, FPGA Advantage and Synplicity. Followed D0-254 standards.
  Verified Xilinx Vertex II Pro FPGA using VHDL, Verilog, TCL,Modelsim for Image Processing Board in aircraft.

• Consultant

  Freescale Semiconductor

  (Public Company; 10,001 or more employees; Semiconductors industry)

  May 2006 — August 2006 (4 months)

  verified microcontroller for Automotive industry that used dual PowerPC microprocessors using verilog.

• Electrical Engineer (Contractor)

  Zaiq Corporation

  (Computer Hardware industry)

  January 2005 — August 2005 (8 months)

• Electrical Engineer (Contractor)

  Intel Corporation

  (Public Company; 10,001 or more employees; intc; Computer Hardware industry)

  July 2001 — December 2001 (6 months)

  • Created test vectors for verilog model of DSL modem with PCI, USB and SCI interface using ModelSim. Prepared verilog netlist of Xilinx Vertex 2000 FPGA. Used Linux shell environment for simulation platform.

• Electrical Engineer (Contractor)

  ATI

  (Public Company; 1001-5000 employees; AMD; Computer Hardware industry)

  June 2000 — June 2001 (1 year 1 month)

  • Created verification tests for 12 million gate Graphics Processor ASIC using Verilog, VHDL and Visual C++.

• Electrical Engineer (Contractor)

  Instrinsix

  (Computer Hardware industry)

  1997 — 1999 (2 years)

• Vice-chair

  IEEE Consultants Network

  (Non-Profit; 51-200 employees; Computer Hardware industry)

  January 1995 — December 1999 (5 years)

  I organized and supported the chair in running the volunteer meetings as well
  as the lecture series. I also took care of mailings, directory printings and membership renewals.

• Electrical Engineer (Contractor)

  Nortel Networks

  (Public Company; 10,001 or more employees; nt; Computer Hardware industry)

  January 1999 — November 1999 (11 months)

  • Created and simulated Verilog board model of OC192 10 Gigabit Sonnet / Ethernet line card including 5 million gate array IBM 0.18 um ASIC on ASIC-Alliance TestbenchPlus environment, C and PLI, Motorola MPC801 Processor.

• Electrical Engineer (Contractor)

  stratus computer

  (Public Company; 1001-5000 employees; Computer Hardware industry)

  January 1998 — December 1998 (1 year)

  • Wrote and implemented verification test plan to verify verilog models of I/O adaptor cards for Chip Express ASIC that interfaced 68030 processor to Serial Communications Controller.

• Electrical Engineer (Contractor)

  BBN

  (Public Company; 1001-5000 employees; Computer Hardware industry)

  January 1997 — December 1997 (1 year)

  • Wrote and implemented verification test plan to test out NEC 250,000 gate ASIC that arbitrated among 15 ports in 50 gigabit ATM router using Cadence VerilogXL, Chronologic VCS, Signalscan on Ultrasparc workstation.

• Consultant

  Tellabs

  (Public Company; 51-200 employees; Computer Hardware industry)

  November 1995 — July 1996 (9 months)

  Simulated and verified in Verilog DSP ASIC for mini-cell
  cellular system.

• Electrical Engineer (Contractor)

  chipcom corporation

  (Public Company; 201-500 employees; Computer Hardware industry)

  January 1993 — December 1994 (2 years)

  • Created and simulated Ethernet, Token-ring bridge board models using Mentor 8.2 Quicksim, Actel FPGA, TI ASIC, LMC, 68302 and 80960 processors, AMD 7990 LAN chip and LM1000 hardware modeler.
  • Programmed in AMPLE and LMC PCL code for 80960 processor.

• Electrical Engineer (Contractor)

  IBM

  (Public Company; 10,001 or more employees; IBM; Computer Hardware industry)

  January 1992 — October 1992 (10 months)

  • Gigabit SONET fiber optic WAN/LAN project.
  • Created and simulated Gigabit SONET fiber optic LAN board model. Used Valid (Cadence), Synopsys, VHDL on AIX IBM RS6000 system. Participated in LAN board lab debug.

• Electrical Engineer (Contractor)

  NCR

  (Public Company; 10,001 or more employees; NCR; Computer Hardware industry)

  January 1991 — August 1991 (8 months)

  • Simulated 150,000 date array, 1.0 micron CMOS, 208 pin flat pack. Gate array interfaces to C710 SCSI I/O processor to Microchannel bus. Gate array was successfully debug and working in 2 weeks in lab.

• Electrical Engineer

  Digital Equipment Corporation

  (Public Company; 10,001 or more employees; HPC; Computer Hardware industry)

  January 1984 — October 1990 (6 years 10 months)

  • Designed, schematic captured, simulated and debugged Toshiba 3200 gate array, 1.5 micron 68 pin grid for Vaxcluster CI Switch. Received patent #4,897,833 for array that arbitrates 8 nodes. Used CAE2000 schematic capture system. Simulated using DECSIM. Timing verified using AUTODLY. Achieved fault coverage of 97%. Designed NTSC/PAL decoder board for interactive video information system. Investigated other video technologies for multimedia IVIS.

Ronald Goodstein’s Education

• Boston University

  MS, Computer Science, 1992 — 1999

• Syracuse University

  BS, Electrical Engineering

Additional Information

Ronald Goodstein’s Websites:

• My Website
• IEEE Consultants Network

Ronald Goodstein’s Interests:

hiking, sailing, bicycling

Ronald Goodstein’s Groups:

IEEE - www.ieee.org
DASC - Design Automation Standards Committee

•    Semiconductor Professional's Group member
•    DEC Alumni member
•    ESL Architects member
•    The DEC Connection member
•    ASIC & FPGA Engineers member

Ronald Goodstein’s Honors:

IEEE Senior Member
Patent #4,897,833 - Hierarchical arbitration system - Digital Equipment Corporation

Ronald Goodstein’s Contact Settings

Interested In:

• career opportunities
• consulting offers
• new ventures
• job inquiries
• expertise requests
• reference requests
• getting back in touch