CTO Office: Semiconductor management at ST-Ericsson
Lyon Area, France
CTO Office: Semiconductor management at ST-Ericsson
Lyon Area, France
16 years experience in the semiconductor industry with varied roles in process nodes from 500 to 32nm. Significant experience and knowledge in low power methodologies, technology and low power design along with overall design flow and SoC implementation. Good management experience with both direct line and functional reporting across sites, groups and technical expertise.
Chip implementation, low power, enthusiasm and drive
(Public Company; Telecommunications industry)
October 2009 — Present (3 months)
Member of CTO Office with overall responsability for semiconductor technology at ST-Ericsson
(Public Company; Telecommunications industry)
August 2008 — September 2009 (1 year 2 months)
ST-Ericsson Joint Venture representative to the IBM/ISDA 32/28nm process alliance.
Responsible for rolling out the ISDA 32/28nm process technology to the ST-Ericsson joint venture. Working with IBM/ISDA Alliance partners and ST Microelectronics to put together the best in class 32/28nm process and design implementation technologies.
Also design manager for ST-Ericsson responsible for implementation teams over 4 sites working on multiple projects.
Responsible for:-
STA
Synthesis
Floorplanning
Physical Implementation
CTS
Timing Closure
Manufacturing checks
Final GDSII
Package Co-design
(Public Company; 10,001 or more employees; TXN; Semiconductors industry)
January 2004 — August 2008 (4 years 8 months)
Team lead of physical design/timing closure/sta team working on TI's 45nm products.
Responsible for:-
STA
Synthesis
Floorplanning
Physical Implementation
CTS
Timing Closure
Manufacturing checks
Final GDSII
(Semiconductors industry)
1993 — 2004 (11 years )
Various roles in physical design from stdcell and IO design to full chip RTL2GDSII creation and closure. EDA and methodology along with pre sales and customer facing roles and applications engineering.