Robert Lombardi

Current

• Staff Design Engineer at Toshiba America Electronic Components

Past

• Design Engineer at Quicksilver
• Design Engineer at White Eagle Systems

Education

• San Jose State University

Recommended

2 people have recommended Robert

Connections

50 connections

Industry

Computer Hardware

Robert Lombardi’s Summary

Started at White Eagle Technologies doing everything from profiling DSP algorithms, to implementing coprocessors in Verilog and verifying behavior in simulation and on FPGA's.

Now working at Toshiba America Electronic Components (TAEC) with the main responsibility of supporting the usage of EDA tools for our Design Center engineers. Currently supporting tools for synthesis, static timing analysis (STA), formal verification, design for test (DFT), simulation and internal tools. Also working within TAEC and with Toshiba Japan to make improvements.

Involved with verification challenges for System On Chip projects. Using VERA, Verilog and C to verify IP's.

Also enjoy technical writing with Framemaker, creating user manuals and specifcations that are used within Toshiba and with our customers.

Robert Lombardi’s Specialties:

Verilog / VHDL design and verification. Static Timing Analysis (STA), Formal Verification, Design for Test (DFT)

Robert Lombardi’s Experience

• Staff Design Engineer

  Toshiba America Electronic Components

  (Public Company; 10,001 or more employees; Semiconductors industry)

  July 2002 — Present (6 years 2 months)

  System On Chip Verification using VERA, Verilog. Integration with ARM processors.
  
  EDA support for Static Timing analysis (STA), Verilog and VHDL simulation, Formal Verification, Design For Test (DFT), and internal tools.
  
  Six Sigma project leader to reduce support turn around time (TAT)
  
  Research and evaluation of new tools and technologies.

• Design Engineer

  Quicksilver

  (Privately Held; 51-200 employees; Computer Hardware industry)

  April 2000 — April 2002 (2 years 1 month)

  - Designer, developer of a process and flow automation tool which targeted to provide automation from RTL to GDS.
  - Designer, developer of the AMA Elaborator, which provided parameters for Verilog or SystemC. Allowing parameterization for the number of instances, ports, connections, port widths and more. This assisted us to have a quickly adaptable architecture with respect to core computational elements such as alu’s, multipliers, filters or other specialized elements.
  - Managed MySQL database.
  - Published User Manuals.
  - Customer support.
  - System and Unit level hardware implementation and verification using Verilog, Perl, Assembly, and C++
  - Implemented AHB master and slave test modules.

• Design Engineer

  White Eagle Systems

  (Privately Held; 1-10 employees; Computer Hardware industry)

  June 1999 — June 2000 (1 year 1 month)

  - Performed “hot spot” analysis on a GSM EFR DSP algorithm. Designed, implemented and verified a co-processor for accelerating FIR and IIR operations.
  
  - Designed, implemented and verified an AHB DMA interface for use by the co-processor
  
  - Used Xilinx FPGA’s to verify the coprocessor along side an ARC processor. Co-processor provided over 2X speed improvement to GSM EFR.

Robert Lombardi’s Education

• San Jose State University

  Bachelor, Computer Engineering, January 1991 — January 2000

Robert Lombardi’s Contact Settings

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