Design Engineer at Silvan Innovation Labs
Bangalore Area, India
Design Engineer at Silvan Innovation Labs
Bangalore Area, India
(Privately Held; Consumer Electronics industry)
September 2009 — Present (3 months)
(Educational Institution; 10,001 or more employees; Higher Education industry)
August 2008 — May 2009 (10 months)
I was responsible for conducting 4 hours of recitations of Algebra & Trigonometry course (MA159 during fall-2008) and Single Variable Calculus (MA162).
(Educational Institution; 10,001 or more employees; Higher Education industry)
June 2008 — August 2008 (3 months)
Students' Rating: 4.8 out of 5
Taught the conplete course, and was responsible for class-slides, quizzes, examinations and projects. Supervised an Undergraduate Teaching Assistant. Developed and maintained content for course web-site.
(Research industry)
August 2007 — May 2008 (10 months)
Students' Rating: 4.2 out of 5 (Average of rating in 3 sections)
Main responsibilities included teaching recitation sections, conducting weekly quizzes, preparing questions for examination, developing lab. as well as project material on JavaScript & HTML.
(Public Company; 1001-5000 employees; LSI; Semiconductors industry)
July 2006 — July 2007 (1 year 1 month)
Worked as Design Engineer I in IO Design Team. Designed a family of 65nm IO cells using CADENCE Tools and LSI specific design flow. Actively supported 90nm IO cells using HSPICE. Working on 90 nano-meter technology, characterized the IO cells for slew rate 1.8 Volt LVCMOS family.
(Public Company; 1001-5000 employees; BRCM; Semiconductors industry)
January 2006 — June 2006 (6 months)
Worked with Verification team and developed Perl Scripts for coverage report parsing and generating Verilog Code for register-slamming. Simulated different functionalities and generated Verilog Coverage Report using VERA. Supported both design & verification teams creating HTML interface.
(Research industry)
May 2004 — July 2004 (3 months)
- Worked in a team of four trainees.
- Implemented a part of ongoing project in Reactor Control Division.
MS , ECE , 2007 — 2009
CGPA : 3.84
Course Work:
1. Random Variables & Signals
2. Information Theory & Source Coding
3. Real Analysis
4. Estimation & Detection Theory
5. Digital Communications
6. Digital Signal Processing
7. Computational Models & Methods
8. Error Correcting Codes
9. Introduction to Entrepreneurship & Innovation
THESIS: AN INVESTIGATION OF REVERSIBLE VARIABLE LENGTH CODES
A reversible variable length code(RVLC) is used as an entropy encoding technique in major audio-video compression standards. A detailed investigation of RVLC construction algorithms is carried out and two algorithms are proposed. A novel analogy, virus-victim analogy, is also developed to establish relationship between prefix-free codes and RVLCs.
BE , Electrical & Electronics Engineering , 2002 — 2006
CGPA: 9.46 out of 10
Relevant Course Work:
Digital Signal Processing
Communications System
Image Processing
Digital Electronics & Computer Organization
Data Communications & Networks
Microprocessor programming and Interface
Advanced Digital VLSI Design
Telecommunication Switching System & Networking
Joint Source Channel Coding, Variable Length Codes, Algorithms