Nigamanth Lakshminarayana

Current

Senior Staff Engineer at Broadcom India

Past

Staff Engineer at Broadcom India
Systems Architect at Agere Systems Inc.
ASIC Design Engineer at Agere Systems Inc

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Education

XLRI Jamshedpur
University of North Carolina at Charlotte
Bangalore University

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Recommended

5 people have recommended Nigamanth

Connections

168 connections

Industry

Semiconductors

Websites

IEEE Spectrum Article

Nigamanth Lakshminarayana’s Summary

Seven years hands-on experience in the design of multi-million gate ASICs and standard products. Well versed with all aspects of the ASIC design flow and direct exposure to architecture and verification, DFT, functional and timing analysis and physical design.

Past and Present responsibilities include

- Top level integration in Network Switching Products (65/130 nm) focusing on power up reset sequence, clocking policies, Analog IP (Serdes/PLL) integration, IO padring, straps and package requirements, top level design and connectivity, top level IO constraints, lint and synthesis scripts and timing closure. Top level documentation and Board level System Design Kit requirements for each switching product.

- Post silicon validation of a Network Switch Product (Board level bringup) verifying functionality and basic switching features.

- Integration of a four lane PCI Express Core/Serdes and top level reset sequence design in a Ethernet switch

- Architecture of multi-disk Serial ATA (SATA) controller interfacing between a RAID5 controller and HDDs in a media streaming NAS product. Involved in verification of the design using specman 'e' and Post silicon validation of the SATA controller with disk drives from multiple vendors.

- Backend Lead for mulit-million gate Network Processor/Ethernet ASICs. Owned constraints, synthesis scripts and synthesis/placement of two 200K+ blocks using Physical Compiler. Integrated DFT features (BSCAN, MBIST, LSSD), IO macros and clock/reset structures. ATE support and generation of functional/test ATE vectors.

Nigamanth Lakshminarayana’s Specialties:

Chip Architecture, Verification, Synthesis, DFT, Timing closure, Integration and Design

Nigamanth Lakshminarayana’s Experience

Senior Staff Engineer

Broadcom India

(Public Company; 1001-5000 employees; BRCM; Semiconductors industry)

April 2007 — Present (2 years 8 months)

Integration of PCI express core in a Network Switch, powerup reset sequence, synthesis and timing closure at block level.

Owning design of external CPU management interface to the Ethernet switch
Staff Engineer

Broadcom India

(Public Company; 1001-5000 employees; BRCM; Semiconductors industry)

September 2005 — April 2007 (1 year 8 months)

Staff Engineer, Tech Lead

Primary focus on Chip Integration, clocking and reset strategy, synthesis and timing closure.
Systems Architect

Agere Systems Inc.

(Public Company; 5001-10,000 employees; AGR; Semiconductors industry)

January 2004 — September 2005 (1 year 9 months)

System and chip level architecture, verification and validation of media streaming NAS systems.

Involved in defining the architecture and integration of SATA controller, verification using specman 'e', emulation and post-silicon bringup.

Co-applicant of two patents in this area pending approval.
ASIC Design Engineer

Agere Systems Inc

(Public Company; 1001-5000 employees; AGR; Semiconductors industry)

January 2001 — December 2003 (3 years )

Backend Lead for multi-million gate Network Processor/Ethernet PHY ASICs.

Owned constraints and synthesis of two 200K+ blocks using physical compiler. Involved in clock/reset methodology, insertion of DFT features (Bscan, Muxed-scan and MBIST).

Co-ordinated with physical design engineer and assisted in timing closure.

ATE vector generation and support.

Nigamanth Lakshminarayana’s Education

XLRI Jamshedpur

PGCBM , Business Management , 2008 — 2009
University of North Carolina at Charlotte

M.S. , Electrical and Computer Engineering , 1999 — 2000

Graduate Research Assistant,
Cameron Applied Research Center,
UNC-Charlotte

Research in the area of semiconductor processing. Growth of SiGe heterostructures using molecular beam epitaxy, analysis using AFM, SEM and Electron Microscope.

• Thesis titled "Bandgap Engineering of Source Drain Structures."

• Paper publications and poster presentations in AVS conferences.

• Recipient of travel and academic scholarships in the line of research.
Bangalore University

B.E. , Instrumentation and Electronics , 1994 — 1998

Internship at LRDE Bangalore as part of the curriculum in the final year

"Radar Target and Noise Simulator" - awarded the second prize in the department