
Owner/Senior Design Engineer, Sagetek Consulting, LLC
Greater Denver Area

Owner/Senior Design Engineer, Sagetek Consulting, LLC
Greater Denver Area
ASIC front-end design and verification consultant. Experienced from conception to prototype debug including architecture, HDL design, testbench and vector development, synthesis, SOC integration, STA, and DFT.
CAD Tools Sets: Cadence, Synopsys, MAGMA, Mentor Graphics, IKOS
Languages: Verilog, SystemVerilog, VHDL, CSH, C, Perl, HTML, PLI, TCL, Python
Simulation: VCS, NCSim, Modelsim, Verilog-XL, Silos, Summit Visual HDL
Static Timing: Primetime
DFT: TetraMax, Fastscan, TestKompress
FPGA: Synplicity, Xilinx
Assertions: SystemVerilog, 0in
Formal Training: AT/IDE, SCSI, SSA, 1394, Disk Drive Technology, Servo Technology, PRML, LSI Flexstream tool flow, MAGMA Blast Create,SystemVerilog
(Sole Proprietorship; Semiconductors industry)
2000 — Present (9 years )
ASIC front-end experience from conception to prototype debug including architecture, HDL design, testbench and vector development, SOC integration, synthesis, STA, and DFT.
(Self-Employed; Internet industry)
1996 — Present (13 years )
Developed several websites for clients. Graphic design for CD packaging and promo material. Familiar with Adobe (Photoshop, Dreamweaver), Macromedia Homesite, Quark and Quicktime software. I have experience with video and music editing and online store setup. Google website tools including Adwords, Adsense, and Feedburner.
(Public Company; lsi; Semiconductors industry)
2008 — 2009 (1 year )
Developed fully programmable disk drive model in SystemVerilog for use within customer’s SOC testbench environment. Assisted in SOC testbench development.
(Public Company; TAD; Semiconductors industry)
2007 — 2007 (less than a year)
Chip synthesis of a 130nm design. Timing analysis. Real-time synthesis and simulation results posted to web page.
(Public Company; 10,001 or more employees; MSFT; Semiconductors industry)
2006 — 2006 (less than a year)
Worked with analog circuit designer to architect, design and integrate digital support logic surrounding an analog pixel array circuit for a test chip.
(Public Company; 1001-5000 employees; Semiconductors industry)
2006 — 2006 (less than a year)
CPLD to ASIC conversion of a small Drum controller design.
(Privately Held; 501-1000 employees; Semiconductors industry)
2004 — 2005 (1 year )
DFT and IDE development.
(Public Company; 10,001 or more employees; TI; Semiconductors industry)
2003 — 2004 (1 year )
Chip-level and IDE test development.
(Privately Held; 1001-5000 employees; Semiconductors industry)
2002 — 2003 (1 year )
Miscellaneous SOC integration and testing.
(Public Company; 5001-10,000 employees; ADPT; Semiconductors industry)
2001 — 2002 (1 year )
Chip-level synthesis, static timing analysis, and Scan/JTAG insertion for a SATA RAID controller.
(Public Company; 10,001 or more employees; Semiconductors industry)
2000 — 2001 (1 year )
Static Timing Analysis of six designs.
(Public Company; 10,001 or more employees; Semiconductors industry)
1999 — 2000 (1 year )
TPA Division (formerly Adaptec’s Peripheral Technology Solutions Department). Predominantly worked on next-generation IDE target interface design. Participated in company's Reusable Design initiative.
(Public Company; 1001-5000 employees; ADPT; Semiconductors industry)
1995 — 1999 (4 years )
Target IDE design and test.
(Public Company; 10,001 or more employees; NCR; Semiconductors industry)
1993 — 1995 (2 years )
Microelectronic Products Division (a.k.a. AT&T GIS, Symbios, Hyundai)
Designed the DMA interface, capable of automated SSA SCSI message handling, of industry’s first SSA data controller chip.
(Government Agency; 1001-5000 employees; Research industry)
1991 — 1991 (less than a year)
MS , Electrical Engineering , 1991 — 1993
BS , Electrical Engineering Technology , 1987 — 1991
Music, Outdoors, Travel, Sports, Energy Medicine
IEEE, SWE
Patent No. 5,613,136, Locality Manager Having Memory and Independent Code, Bus Interface Logic, and Synchronization Components for a Processing Element for Intercommunication in a Latency Tolerant Multiple Processor, March 1997