Owner/Senior Design Engineer, Sagetek Consulting, LLC
Fort Collins, Colorado Area
- Current
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- Consultant at LSI
- Owner at Sagetek Consulting, LLC (Sole Proprietorship)
- Website and Graphic Designer (Self-employed)
- Past
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- Consultant at Tandberg Data
- Consultant at Microsoft
- Consultant at Exabyte
- Consultant at Digeo
- Consultant at Texas Instruments
- Consultant at Digeo
- Consultant at Adaptec
- Consultant at LSI Logic
- Staff Engineer I at STMicroelectronics
- ASIC Design Engineer at Adaptec
- ASIC Design Engineer at NCR
- Summer Intern at Stanford Linear Accelerator Center
- Education
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- University of Iowa
- Texas Tech University
- Recommended
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3 people have recommended Michelle - Connections
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98
connections
- Industry
- Semiconductors
- Websites
Michelle Hopkins’s Summary
Michelle is a senior ASIC Design Engineer and the owner of Sagetek Consulting, LLC. Sagetek provides ASIC and FPGA design and test services. We assist our clientele with the conception, design and test of integrated circuits. Sagetek provides consulting services in addition to employee referrals to semiconductor companies.
Michelle Hopkins’s Specialties:
CAD Tools Sets: Cadence, Synopsys, MAGMA, Mentor Graphics, IKOS
Languages: Verilog, SystemVerilog, VHDL, CSH, C, Perl, HTML, PLI, TCL, Python
Simulation: VCS, NCSim, Modelsim, Verilog-XL, Silos, Summit Visual HDL
Static Timing: Primetime
DFT: TetraMax, Fastscan, TestKompress
FPGA: Synplicity, Xilinx
Assertions: SystemVerilog, 0in
Formal Training: AT/IDE, SCSI, SSA, 1394, Disk Drive Technology, Servo Technology, PRML, LSI Flexstream tool flow, MAGMA Blast Create,SystemVerilog
Michelle Hopkins’s Experience
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Consultant
LSI
(Public Company; 5001-10,000 employees; Semiconductors industry)
2008 — Present (less than a year)
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Owner
Sagetek Consulting, LLC (Sole Proprietorship)
(Sole Proprietorship; Semiconductors industry)
2000 — Present (8 years)
ASIC front-end experience from conception to prototype debug including architecture, HDL design, testbench and vector development, SOC integration, synthesis, STA, and DFT.
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Website and Graphic Designer
Self-employed
(Self-Employed; Graphic Design industry)
1996 — Present (12 years)
Developed several websites for clients predominantly within the music industry. Graphic design for CD packaging and promo material. Familiar with Adobe (Photoshop, Dreamweaver), Macromedia Homesite, Quark and Quicktime software. I have experience with video and music editing and online store setup.
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Consultant
Tandberg Data
(Public Company; TAD; Semiconductors industry)
2007 — 2007 (less than a year)
Chip synthesis of a 130nm design. Timing analysis. Real-time synthesis and simulation results posted to web page.
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Consultant
Microsoft
(Public Company; 10,001 or more employees; MSFT; Semiconductors industry)
2006 — 2006 (less than a year)
Worked with analog circuit designer to architect, design and integrate digital support logic surrounding an analog pixel array circuit for a test chip.
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Consultant
Exabyte
(Public Company; 1001-5000 employees; Semiconductors industry)
2006 — 2006 (less than a year)
CPLD to ASIC conversion of a small Drum controller design.
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Consultant
Digeo
(Privately Held; 501-1000 employees; Semiconductors industry)
2004 — 2005 (1 year)
DFT and IDE development.
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Consultant
Texas Instruments
(Public Company; 10,001 or more employees; TI; Semiconductors industry)
2003 — 2004 (1 year)
Chip-level and IDE test development.
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Consultant
Digeo
(Privately Held; 1001-5000 employees; Semiconductors industry)
2002 — 2003 (1 year)
Miscellaneous SOC integration and testing.
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Consultant
Adaptec
(Public Company; 5001-10,000 employees; ADPT; Semiconductors industry)
2001 — 2002 (1 year)
Chip-level synthesis, static timing analysis, and Scan/JTAG insertion for a SATA RAID controller.
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Consultant
LSI Logic
(Public Company; 10,001 or more employees; Semiconductors industry)
2000 — 2001 (1 year)
Static Timing Analysis of six designs.
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Staff Engineer I
STMicroelectronics
(Public Company; 10,001 or more employees; Semiconductors industry)
1999 — 2000 (1 year)
TPA Division (formerly Adaptec’s Peripheral Technology Solutions Department). Predominantly worked on next-generation IDE target interface design. Participated in company's Reusable Design initiative.
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ASIC Design Engineer
Adaptec
(Public Company; 1001-5000 employees; ADPT; Semiconductors industry)
1995 — 1999 (4 years)
Target IDE design and test.
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ASIC Design Engineer
NCR
(Public Company; 10,001 or more employees; NCR; Semiconductors industry)
1993 — 1995 (2 years)
Microelectronic Products Division (a.k.a. AT&T GIS, Symbios, Hyundai)
Designed the DMA interface, capable of automated SSA SCSI message handling, of industry’s first SSA data controller chip. -
Summer Intern
Stanford Linear Accelerator Center
(Government Agency; 1001-5000 employees; Research industry)
1991 — 1991 (less than a year)
Michelle Hopkins’s Education
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University of Iowa
MS, Electrical Engineering, 1991 — 1993
- Activities and Societies:
- IEEE, SWE
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Texas Tech University
BS, Electrical Engineering Technology, 1987 — 1991
- Activities and Societies:
- Tau Alpha Pi
Additional Information
Michelle Hopkins’s Websites:
Michelle Hopkins’s Interests:
Music, Outdoors, Travel
Michelle Hopkins’s Groups:
IEEE, SWE
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KIVA -
American Red Cross -
ASIC & FPGA Engineers
Michelle Hopkins’s Honors:
Patent No. 5,613,136, Locality Manager Having Memory and Independent Code, Bus Interface Logic, and Synchronization Components for a Processing Element for Intercommunication in a Latency Tolerant Multiple Processor, March 1997
Michelle Hopkins’s Contact Settings
Interested In:
- consulting offers
- job inquiries
- expertise requests
- reference requests
- getting back in touch
