Ph.D., Senior Design Engineer, Integrated Circuits at Altera Corporation
San Francisco Bay Area
Ph.D., Senior Design Engineer, Integrated Circuits at Altera Corporation
San Francisco Bay Area
I design semiconductor memory at the transistor level. I am currently designing SRAM for Altera's high-performance Stratix FPGA family. My Ph.D. research was in techniques to reduce power consumption in content-addressable memory (CAM) for networking applications.
(Public Company; 1001-5000 employees; ALTR; Semiconductors industry)
July 2006 — Present (2 years 5 months)
I design embedded SRAM for the high-performance Stratix FPGA product family.
(Non-Profit; 201-500 employees; Semiconductors industry)
April 2006 — Present (2 years 8 months)
Technical editing of papers accepted for publication in the digest (conference proceedings) of the International Solid-State Circuits Conference, held every February in San Francisco.
(Educational Institution; 5001-10,000 employees; Higher Education industry)
January 2000 — April 2005 (5 years 4 months)
I was Head Tutorial Teaching Assistant (TA) in 2002-2005 for a third year undergraduate electronics course on single-stage amplifiers, cascoding, differential amplifiers, frequency response of amplifiers, and compensation.
I was Head Tutorial Teaching Assistant in 2001-2003 for a third year undergraduate digital electronics course on equivalent resistance, understanding transistor parasitic capacitances, design of logic gates and sequential circuits, and introduction to SRAM, DRAM, and CAM memories.
I was Head Tutorial Teaching Assistant in 2004 for a 4th year undergraduate course in computer architecture on pipelining, hazards, dynamic scheduling, branch prediction, and caches. The course labs used the SimpleScalar simulator.
I also was a lab TA for a 4th year undergraduate VLSI design course and a 2nd year undergraduate introductory course in digital design, both in 2000.
(Privately Held; 11-50 employees; Semiconductors industry)
May 1999 — August 1999 (4 months)
My main job was functionally verifying a content-addressable memory (CAM) macro using switch-level simulation.
(Public Company; 10,001 or more employees; NT; Semiconductors industry)
May 1997 — August 1998 (1 year 4 months)
Designed an embedded memory test chip incorporating several compiled memories. Maintained and upgraded Perl-based in-house memory compiler for front-end compiled memory views. Functionally verified RTL portion of a content-addressable memory (CAM) chip.
Ph.D., Electrical Engineering (Electronics), 2001 — 2006
Dissertation title "Design of Low-Power Content-Addressable Memories"
M.A.Sc., Electrical Engineering, 1999 — 2001
B.A.Sc., Engineering Science (Computer Option), 1994 — 1999
Professional experience year (16-month internship) at Nortel in the Memory Development group from May 1997 to August 1998.
SRAM design, DRAM design, non-volatile memory, FPGA building-block design
International Solid-State Circuits Conference (ISSCC) Technical Digest Editor.
2005 Teaching Assistant Award, Dept. of Electrical and Computer Engineering, University of Toronto. Awarded by popular vote of undergraduate students.
2003 Teaching Assistant Award, Dept. of Electrical and Computer Engineering, University of Toronto. Awarded by popular vote of undergraduate students.
2002 Teaching Assistant Award, Dept. of Electrical and Computer Engineering, University of Toronto. Awarded by popular vote of undergraduate students.
2004-2005 Ontario Graduate Scholarship in Science and Technology (OGSST).
2002–2004 Natural Sciences and Engineering Research Council of Canada (NSERC) PGS B Scholarship.
2000–2002 Natural Sciences and Engineering Research Council of Canada (NSERC) PGS A Scholarship.
1999–2000 Ontario Graduate Scholarship in Science and Technology (OGSST).