Julian Fields

Current

Verilog, design, verification of asic / integrated circuits, computer systems design / architecture at Alopatek, Inc

Past

Verilog integrated circuit design / asic verification engineer consultant at National Semiconductor
System simulation and verification engineering consultant at CISCO SYSTEMS
ASIC design and verification consultant (contractor) at Apple Computer

ASIC design engineer (contractor) at Quantum
Verilog and Spice design engineering (consultant) at Loral Rolm Mil Spec Computer
ASIC lead design engineer (contractor) at Acuson bought by Siemens
ASIC Cad engineer (consultant) at Silicon Graphics
Verilog (TM) system simulation engineer (contractor) at Loral Rolm Mil Spec Computer
FPGA Design Engineer /simulation (contractor) at Andros Analyzers
CMOS VLSI logic design engineer at APPLE COMPUTER
ASIC, Gate Array, Board debug, CAD Engineer at Quantum
Chip / computer system design at Too many companies to list
Computer software architect consultant at Transimage
VLSI CMOS ASIC standard cell and gate array design engineer (consultant) at International Microcircuits Inc
Memory Circuit Design Engineer at NATIONAL SEMICONDUCTOR
CMOS IC design engineer full custom at Harris Corporation

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13 more...

Education

Clemson University

Recommended

3 people have recommended Julian

Connections

201 connections

Industry

Semiconductors

Websites

My Company

Julian Fields’s Summary

Julian Fields is an Integrated Circuit Design Architect Consultant for various Silicon Valley companies. 790/800 on Math SAT
(Standard Aptitude Test).
I've been designing a lot of products coming
out of Silicon Valley and other places since 1980.

Julian Fields’s Specialties:

Integrated circuit ASIC and full custom design
and verification and computer system architecture.
Verilog (tm) design and
logic synthesys. System design / computer architecture. Since year 1980. julianfields at the domain yahoo dot com

Julian Fields’s Experience

Verilog, design, verification of asic / integrated circuits, computer systems design / architecture

Alopatek, Inc

(Privately Held; Myself Only; Computer Hardware industry)

January 1997 — Present (12 years 11 months)

Verilog design (TM) and verification contracting.
See http://alopatek.freeyellow.com for full resume.
Also, EEPROM and SRAM memory design engineering and
SPICE circuit simulation/design.
Verilog integrated circuit design / asic verification engineer consultant

National Semiconductor

(Public Company; 1001-5000 employees; nsm; Semiconductors industry)

September 2000 — July 2002 (1 year 11 months)

Consultant. VERILOG (TM) design of physical layer chip /
Vera (TM) verification of a
Gigabit ethernet phy chip (802.3 1000BASE-T).
Responsible for MAC interface , regression farm management using PERL and
platform's LSF.
CVS source control. Vera(tm of Synopsys)
and verilog(tm of Cadence) system simulation. Formal verification equivalence
checking using Chrysalis (tm of Synopsys).
Also designed or verified 3 other chips which used
this as a core.
This is now a standard product (DP83865).
SOC (System on chip) methodology.
System simulation and verification engineering consultant

CISCO SYSTEMS

(Public Company; CSCO; Computer Networking industry)

July 1995 — July 1996 (1 year 1 month)

Simulated model 7200 predator router motherboard and various
boards in Verilog.
This was the new platform that was copied to many
other divisions from the "Core division".
Contained PCI bus, ethernet chips, PCI bridge, etc.
Verilog (TM), Atria, and Synopsys Logic Modeling
(TM) Models.
System simulation using real chips in a
hardware box (LM-1400 or Modelsource (TM)).
Simulation and verification 2 other routers in MARS
Modular Access Router for small office users.
ASIC design and verification consultant (contractor)

Apple Computer

(Public Company; 5001-10,000 employees; AAPL; Computer Hardware industry)

March 1995 — July 1995 (5 months)

Project Firewire:
Worked on 400 Mbps IEEE 1394 Firewire (tm) chip for high speed
networking.
Project Video Game Machine:
Verification, synthesis, design,
and timing analysis of 2 ASICs for Pippin
Power Player.
Verilog interrupt logic design, memory controller testing
Regression setup, source control maintenance.
Synopsys (TM) script writing. Gate level debug. Rebuild Unix
kernel, etc.
Both chips worked first pass.
ASIC design engineer (contractor)

Quantum

(Public Company; 1001-5000 employees; qntm; Computer Hardware industry)

January 1994 — February 1995 (1 year 2 months)

Synopsys (TM) and Verilog (TM) of 2 ASICs.
Gate level sims, synthesis, conversion to TI and Chip Express
gate arrays.
Add timing checks to Verilog sims. Makefiles for synthesis.
PCMCIA block design. Regression testing. My block worked first
pass. Added de-metastability logic.
Verilog and Spice design engineering (consultant)

Loral Rolm Mil Spec Computer

(Public Company; 10,001 or more employees; Defense & Space industry)

December 1992 — July 1993 (8 months)

Synthesis of large high speed gate array.
VHDL, Viewlogic (tm), Synopsys (tm) and LSI Logic CMDE (tm).
VHDL simulation of i860 interface and Crossbar gate arrays.
Multi-Chip Module selection. Spice of board level transmission
lines.
ASIC lead design engineer (contractor)

Acuson bought by Siemens

(Public Company; 1001-5000 employees; acn; Medical Devices industry)

January 1992 — December 1992 (1 year )

Verilog (tm) and Synopsys (tm) of large standard cell from spec.
Sunrise Automatic Test Pattern Generation (ATPG) and boundary
scan design.
Wrote verification, regression scripts, makefiles, source control.
Wrote Synopsys batch queuing program.
C program to handle don't cares. Chip worked first pass.
Used Sun workstation, sole designer engineer on this chip.
ASIC Cad engineer (consultant)

Silicon Graphics

(Public Company; 1001-5000 employees; SGI; Computer Hardware industry)

November 1991 — January 1992 (3 months)

LSI Logic LCAP static timing verification, gate level simulation of 2 gate
arrays.
Floor planning in LSI Logic tools
Debug of Synopsys of Verilog (tm) link problems, etc. Chip worked
1st pass.
Verilog (TM) system simulation engineer (contractor)

Loral Rolm Mil Spec Computer

(Public Company; 1001-5000 employees; Computer Hardware industry)

October 1990 — June 1991 (9 months)

Ikos board level simulation of 1.5 million gate pipelined (ten
gate arrays) computer
Clone of DG MV Eclipse32.
Used Sun workstation. 3 of 4 chips worked first pass.
Synopsys, Verilog(tm), IKOS system simulation of 600,000 gate
board
Design included 5 gate arrays (30K gates to 100K gates).
Teradyne Aida ATPG scan test pattern generation.
Fixed simulation model of RISC Mips R3000 (in house version).
Modeled misc board level components for simulation.
FPGA Design Engineer /simulation (contractor)

Andros Analyzers

(Public Company; 51-200 employees; Computer Hardware industry)

September 1990 — October 1990 (2 months)

Actel field programmable gate arrays: Logic design, and simulated
2 FPGAs.
Orcad draft and VST simulate.
Contained UART, parallel ports, FIFOs, timers, maskable intr.,
for 68000.
Wrote C program to generate test vectors. I got the chips working in time
for the trade show.
CMOS VLSI logic design engineer

APPLE COMPUTER

(Public Company; 501-1000 employees; aapl; Computer Hardware industry)

February 1989 — May 1989 (4 months)

ASIC Design Engineer
Logic simulated 6 VLSI gate arrays inside Macintosh to find
out timing. Taught new users of Mentor Graphics.
ASIC, Gate Array, Board debug, CAD Engineer

Quantum

(Public Company; 501-1000 employees; qntm; Computer Hardware industry)

January 1988 — February 1989 (1 year 2 months)

CONTRACT: QUANTUM: (Jan 1988 - Feb 1989)
ASIC, Gate Array, Board debug, CAD Engineer
Design engineering on a chip and debug of one 1 board.
Helped logic design, test vectors of a disk controller 8,000 gate
array.
Test vectors for an IBM PC/AT interface gate array for high fault
coverage.
Debugged boards containing Intel 8096 microcontroller, SCSI, IBM-PC
bus, and ESDI
Used LSI Logic's LDS 6.2 software on Toshiba's IBM mainframe.
Put together CAE system of Mentor workstations, IKOS workstation,
and VGEN.
Used IKOS fault grading software.
Chip / computer system design

Too many companies to list

(Privately Held; 501-1000 employees; Computer Hardware industry)

June 1985 — May 1988 (3 years )

CONTRACT: CAPSTONE TECHNOLOGY and MEMOREX: (Sept 87- Jan 88)
CONTRACT: VLSI TECHNOLOGY : (July 87) ASIC design
engr
CONTRACT: TRANSIMAGE INC: (a startup) (Jan 86 - Aug 86)
CONTRACT: Pistohl Electronic Tools:
CONTRACT: CALMA-GE: (June 85 - July 1985) CAD tools
ARRAY TECHNOLOGY (a small start-up), San Jose: Jan 84- Jan 85

PAPERS: IEEE JSSC, "A 16k EEPROM with redundancy", Oct 83
Computer software architect consultant

Transimage

(Privately Held; 11-50 employees; Computer Hardware industry)

January 1986 — August 1986 (8 months)

CONTRACT: TRANSIMAGE INC: (a startup) (Jan 86 - Aug 86)
Optical character recognition firmware and microprogramming.
Computer architecture design team to build a custom VLSI
RISC processor
Implemented it in firmware and gate arrays for optical character
recognition
Cross assembled microcode on a DEC VAX using the Microtek Research
assembler.
Real time programming.
Used logic analyzers and Step Engineering emulator.
Debugged Pascal for 68000 using Tektronix 8540 in circuit emulator.
System level simulation for processor performance estimate.
Wrote VAX Pascal routines for TEK-HEX conversion.
Designed schematics for PC board with DRAMS, LED's, switches,
cabling, optics.
Checked plastic design for handheld optical scanner.
VLSI CMOS ASIC standard cell and gate array design engineer (consultant)

International Microcircuits Inc

(Privately Held; 51-200 employees; Semiconductors industry)

August 1983 — December 1983 (5 months)

Logic/circuit design on a 16 by 16 parallel multiplier.
Designed a CMOS standard cell library using Applicon 860.
Redesigned a touch sensor with analog trip points and oscillators
for lamp dimmer.
Memory Circuit Design Engineer

NATIONAL SEMICONDUCTOR

(Public Company; 1001-5000 employees; nsm; Semiconductors industry)

February 1982 — June 1983 (1 year 5 months)

Santa Clara, CA Feb 1982 - June 1983.
CMOS / NMOS Memory circuit design engineer. (involved with 4 chips)
Principal design engineer of 16K NMOS EEPROM (This was sold by
National as a 9817, a competitor to Intel's 2816).
Gained complete understanding of design rules and processing steps.
Designed 10 ms timer, 5V to 30V charge pumps, self test, state
machines
Designed redundancy circuits. All circuits fully on chip. Supervised
layout. The 9817 was a breakthrough chip which eliminated need for
external 22V programming supply, timers, and was much easier
to use.
Simulated the above on IBM mainframe. Did a design study
and simulation of nonvolatile static RAM (NOVRAM) which is a SRAM
with EEPROM inside to restore SRAM contents when power is lost.
CMOS IC design engineer full custom

Harris Corporation

(Public Company; 5001-10,000 employees; Computer Hardware industry)

May 1980 — February 1982 (1 year 10 months)

(involved in 6 chips)
Standard cell library: Designed and laid out library for public
domain router MP2D
74HC00 Series: designed and laid out 4 chips using Calma GDS2.
Designed PLA of CPU Chip.
Spice: Used to design TTL buffers / standard cell library.
Programming: Wrote BASIC and FORTRAN statistics programs.

Julian Fields’s Education

Clemson University

BS , Electrical and computer engineering , August 1977 — December 1980

Activities and Societies:

Treasurer, IEEE Student Chapter-Treasurer,
Varsity Wrestling,
Officer in Honor Fraternity.