J.J. Barrow

Education

• University of Maryland College Park

Recommended

1 person has recommended J.J.

Connections

65 connections

Industry

Computer Hardware

J.J. Barrow’s Summary

Hardware Engineer experienced in research and development of data communications and I/O processing systems.

Awarded six US Patents, work experience includes: project leadership, FPGA and CPLD logic design, IA-32 and PowerPC based board level architecture and design, HW/SW integration, system bring up, product qualification and performance analysis.

Additional Information

J.J. Barrow’s Groups:

IEEE Computer Society, IEEE Communications Society

•    EMC Alumni Network
•    ASIC & FPGA Engineers: www.ASICForum.com
•    Stratalums

J.J. Barrow’s Contact Settings

Interested In:

• reference requests
• getting back in touch