Jeff Wittich

Jeff Wittich

Cloud Business Development and Marketing at Intel Corporation

Location
San Francisco Bay Area
Industry
Semiconductors

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Jeff Wittich's Overview

Current
Past
Education
Connections

396 connections

Websites

Jeff Wittich's Summary

Experienced engineer in the semiconductor industry with expertise in product marketing strategy, product design and development, deep submicron semiconductor device physics, reliability physics and modeling, design of experiments, data analysis, and structured problem solving.

Has excelled in a wide array of roles at Intel, both as a manager and a senior engineer.

Jeff Wittich's Experience

Cloud Business Development and Marketing

Intel Corporation

Public Company; 10,001+ employees; INTC; Semiconductors industry

May 2014Present (5 months) San Francisco Bay Area

Reliability Engineering Manager

Intel Corporation

Public Company; 10,001+ employees; INTC; Semiconductors industry

June 2012May 2014 (2 years) San Francisco Bay Area

- Manage a team of ten engineers responsible for the reliability of all Xeon Server products and associated companion products; managed all quality and reliability validation activities for product qualification
- Doubled team efficiency by implementing the Scrum process and championed its implementation across the entire organization
- Developed innovative techniques for reliability stresses to produce more accurate results as well as reduce costs

Senior Product Quality and Reliability Engineer

Intel Corporation

Public Company; 10,001+ employees; INTC; Semiconductors industry

June 2009May 2014 (5 years) Santa Clara, CA

- Led Q&R engineering team through product qualification process of multiple 22-nm IA-based multi-core server microprocessors; responsible for managing all Q&R product risks, and qualification plans; worked with technology development to align process and product needs
- Responsible for reliability portion of product qualification for a 32-nm IA-based multi-core server microprocessor; worked with design to develop and simulate circuit and layout improvements; worked with test developers to debug and optimize ATE test program; worked with marketing and customers to understand desired performance and functionality
- Developed mathematical models in order to predict performance, reliability, and yield characteristics of product both in pre and post Silicon phases; set processor specs based on defined reliability goals and customer feedback
- Designed and analyzed experiments to validate reliability models for infant mortality, gate oxide breakdown, and end-of-life performance; optimized testing algorithms and flow for reliability, yield, and Vccmin performance
- Performed reliability verification and design rule checking on areas such as electrostatic discharge (ESD), electromigration, and high voltage I/O circuits; designed HBM and CDM experiments to validate ESD performance; designed, simulated, and laid out circuit improvements for robustness
- Worked with customers to design and evaluate customized solutions to meet individual performance, power, thermal and reliability needs; provided written and verbal communication to them in response to changes in processor specs and performance

Senior Device Engineer

Intel Corporation

Public Company; 10,001+ employees; INTC; Semiconductors industry

June 2005June 2009 (4 years 1 month)

- Utilized device physics expertise as part of team developing the industry’s first high volume logic 45-nm Hi-K, Metal Gate process, and transferred technology to production at record yields. Designed and analyzed experiments to drive performance and yield enhancement in the front end of the line. Reviewed fab-wide process changes prior to implementation.
- Responsible for multiple process start-ups (45, 65, 130 nm nodes) by designing experiments and employing statistically-based data analysis to ensure high performance and yields. Introduced process changes to reduce variation and improve process capability.
- Built data models and determined targets for process parameters in order to meet product requirements. Led team responsible for process control and targeting.
- Leveraged problem solving expertise, data modeling skills, and device measurement techniques to determine root cause for electrical and reliability failures, often by leading ad hoc teams.

Process Engineer

Intel Corporation

Public Company; 10,001+ employees; INTC; Semiconductors industry

June 2004June 2005 (1 year 1 month)

Responsible for maintaining process control through SPC, and proper operation of TEL Unity II Etchers.
Characterized and improved plasma etch process, including Advanced Process Control (APC) features.

Graduate Student Researcher

University of California, Santa Barbara

Educational Institution; 5001-10,000 employees; Higher Education industry

August 2002June 2004 (1 year 11 months)

- Advisor: Umesh Mishra
- Designed, fabricated, and characterized GaN MESFETs.
- Extensive cleanroom fabrication and test hardware experience (HP Semiconductor Parameter Analyzers, CV-Plotter, Curve Tracer, Oscilloscope).

Circuit Design Intern

Intel Corporation

Public Company; 10,001+ employees; INTC; Semiconductors industry

May 2002August 2002 (4 months)

- Responsible for design, optimization, and simulation of system memory predriver cells in order to reduce size and improve performance.
- Set up and ran simulations on voltage level shifter circuit.

Jeff Wittich's Volunteer Experience & Causes

  • Volunteer Interests

    • Causes I care about:

      • Economic Empowerment
      • Education
      • Poverty Alleviation
      • Science and Technology
      • Social Services

Jeff Wittich's Skills & Expertise

  1. Design of Experiments
  2. Data Analysis
  3. JMP
  4. Semiconductors
  5. Device Physics
  6. Physics
  7. Testing
  8. SPC
  9. Simulations
  10. Semiconductor Industry
  11. Silicon
  12. Yield
  13. Circuit Design
  14. Reliability
  15. Reliability Engineering
  16. Debugging

Jeff Wittich's Education

University of California, Santa Barbara

MS, Electrical Engineering

20022004

University of Notre Dame

BS, Electrical Engineering

19982002

Summa Cum Laude

Activities and Societies: Eta Kappa Nu Chapter Secretary, Tau Beta Pi

Bishop Watterson High School

19941998

Jeff Wittich's Additional Information

Websites:
Interests:

marathons, triathlons, mountain biking, snowboarding, financial modeling

Groups and Associations:

IEEE, Tau Beta Pi, Eta Kappa Nu

Contact Jeff for:

  • career opportunities
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  • new ventures
  • job inquiries
  • expertise requests
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  • getting back in touch

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