Jean-Philippe Lambert

Past

• System Architect at Wipro - NewLogic
• Senior Digital Design Engineer at NewLogic
• Senior Consultant at THALES Microelectronics

• Digital Designer at TACHYS
• Senior Consultant at ALTIOR
• Junior Consultant at ALPLOG

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Education

• Universite de Metz - SUPELEC
• Université Henri Poincaré (Nancy I)
• Université Henri Poincaré (Nancy I)

• Université Henri Poincaré (Nancy I)
• Université Henri Poincaré (Nancy I)
• Lycee A.Varoquaux / Tomblaine - France
• Lycee F. Chopin / Nancy - France

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Connections

182 connections

Industry

Semiconductors

Jean-Philippe Lambert’s Summary

I am a hardware engineer with 10+ years experience in RTL coding, 5 years experience in Bluetooth IP/product development, and 4 years in Bluetooth system architecture specification.
For the last 5 years I’ve been working as principal design engineer, technical leader and system architect for Wipro - NewLogic, a leading semiconductor design services provider and supplier of intellectual property (IP) cores for complex wireless and wireline applications.
During this time I’ve also been a member of the Bluetooth SIG Core Specification Working Group.
I specified and designed implementation solutions for Bluetooth controller, ensured development flow process respect, worked with local and foreign business partners and customers, ensuring pre-sales activities and customer support, accommodating the necessary design changes in order the end-product to be successful.
I have an expert knowledge in digital design flow methodologies, design simulation, and full system validation. I have a proven Bluetooth system architecture expertise. I am self-motivated, and an enthusiastic person with strong communication skills. I am not afraid to make decisions and take responsibility. I like to work on complex systems, to solve problems, and I’m able to work in multitasking mode. I am always willing to learn new technologies and perform self-education every day.

Jean-Philippe Lambert’s Specialties:

Bluetooth Low Energy system.
Bluetooth 3.0 + HS system.
Bluetooth 2.1 + EDR system.
Matlab.
Clock / Reset / Power Gating Strategy.
VHDL / Verilog RTL.
DFT / BIST / ATPG.
Simulations.
Synthesis / STA.
Formal Verification.
FPGA Prototyping.
Back-End knowledges (X-talk, IR-DROP, Metal Filling, etc...).

Jean-Philippe Lambert’s Experience

• System Architect

  Wipro - NewLogic

  (Privately Held; Semiconductors industry)

  January 2006 — October 2009 (3 years 10 months)

  WiFi and Bluetooth IP Provider
  Design Service Center
  
  Bluetooth System Architect
  System study on Bluetooth Low energy
  System study on Bluetooth 3.0 (+ HS)
  System and Digital specifications for Bluetooth 2.0/2.1 RF
  System and algorithm study for Bluetooth 2.0/2.1 Modem (Rx path)
  System study, functional and design specifications of Bluetooth 2.1 baseband controller
  Principal Design Engineer role for 2 years
  Front-End Flow enhancement
  RTL Design
  Synthesis
  Formal Verification
  ATPG coverage
  Gate Level Simulations

• Senior Digital Design Engineer

  NewLogic

  (Privately Held; Semiconductors industry)

  October 2004 — January 2006 (1 year 4 months)

  WiFi and Bluetooth IPs provider
  Design Service Center
  
  Bluetooth 1.2 design upgrade
  802.11a/b/g simulations (RTL + gate level)
  GSM product FPGA prototyping

• Senior Consultant

  THALES Microelectronics

  (Public Company; HO; Defense & Space industry)

  October 2002 — October 2004 (2 years 1 month)

  Project in Texas Instruments - Villeneuve-Loubet, France (5 months) / IP division / GSM Products
  => OMAP2430 PRCM design
  
  Project in NewLogic Technologies - Sophia antipolis, France (7 months) / WiFi and Bluetooth IPs provider
  => 802.1a/b SoC simulations
  
  Project in StepMind- Le Cannet - France (12 months) / WiFi IPs provider
  => 802.11a/b simulation and Clock Controller design

• Digital Designer

  TACHYS

  (Privately Held; 11-50 employees; Semiconductors industry)

  January 2002 — September 2002 (9 months)

  SERDES, 10Gbit Ethernet, InfiniBand, PCI Express IPs provider
  => RTL Design, simulation (RTL and gate level) and synthesis tests

• Senior Consultant

  ALTIOR

  (Privately Held; Information Technology and Services industry)

  November 2000 — January 2002 (1 year 3 months)

  Project in TACHYS Technologies, Sophia Antipolis - France (6 months) / SERDES, 10Gbit Ethernet, InfiniBand, PCI Express IPs provider
  => RTL and gate level simulations
  
  Project in PHILIPS Semiconductors, Sophia Antipolis - France (5 months) / Bluetooth Base Band Controller
  => RTL and gate level simulations, formal verification

• Junior Consultant

  ALPLOG

  (Privately Held; 201-500 employees; Information Technology and Services industry)

  July 1999 — November 2000 (1 year 5 months)

  Project in Nipson / Belfort - France: Industrial High Speed Printer Products
  => PCB development (OrCAD), FPGA development, RTL simulations, PCB Board test, and printer machine tests

Jean-Philippe Lambert’s Education

• Universite de Metz - SUPELEC

  PhD , Micro-Electronics , 1995 — 1999

• Université Henri Poincaré (Nancy I)

  DEA I&M , Micro-Electronics , 1994 — 1995

  Modem Architecture Study project : Implementation example onto FPGA

• Université Henri Poincaré (Nancy I)

  Maitrise EEA , Electronics, Electrotechnics, Automatics , 1993 — 1994

  FM@500MHz project using Digital PLL and TV VCO architecture.

• Université Henri Poincaré (Nancy I)

  Licence EEA , Electronics, Electrotechnics, Automatics , 1992 — 1993

• Université Henri Poincaré (Nancy I)

  DEUG SPI , Physics / Electronics , 1990 — 1991

• Lycee A.Varoquaux / Tomblaine - France

  BTS Physicien , Physics , 1988 — 1990

  Training period at Turck Prodassi / Reichert Technology company
  Industrial rolling bridge demonstrator using laser distance meter, position regulator, and an electric train toy.

• Lycee F. Chopin / Nancy - France

  BAC D , Maths / Nature Sciences , September 1987 — June 1988