
Sr. SoC~FPGA~ASIC~Embedded Designer/Consultant
Greater San Diego Area

Sr. SoC~FPGA~ASIC~Embedded Designer/Consultant
Greater San Diego Area
• 20 years in applied R&D with focus on digital, chip-level design & embedded processing
• Full product development cycle with solid system, application & customer perspective
• Self-starting project owner and team lead
• Pragmatic problem solver with extreme attention to detail & passion for excellence
SoC, FPGA, ASIC, Verilog, RTL, Architecture & Partitioning, Logic & Timing Design, IP, MCU/CPU/Firmware, High-Speed I/O and Protocols (SerDes, DDR, QDR, PCIe, ...), Datacom/Telecom
(Privately Held; Semiconductors industry)
March 2009 — Present (10 months)
- Completed a number of Virtex5 (LX220, LX50, SXT50/ML506-Xtreme-DSP-Platform) projects, including: Custom I/O for an embedded, mission-critical, COTS SBC built around Intel Mobile Core i7 architecture; Video capture from a 100fps, 15Mpix, 12-bit high-end camera chip; Data acquisition via PCI Express add-on card for a 64-bit RAID 0 Linux PC
> Completed Intel MindShare training in PCI Express, including Gen2.0 additions
> Completed Altera training in Quartus II tool suite, C2H and PCIe on Arria II GX
(Public Company; Semiconductors industry)
July 2006 — March 2009 (2 years 9 months)
- Architected APB-based (AMBA3.0) control plane for a 4-million gate 10Gbps SR/LR/LRM/KR Ethernet PHY in a 65nm ASIC-like flow. Used 8051 MCU @ 312MHz. Created IEEE802.3 Clause 45 MDIO I/F and solved access concurrency between on-chip and off-chip host. Automated CSR generation using Perl. Wrote interface gaskets for all on-chip modules, including a 32-bit MACsec IP block. Devised transparent, hardware-accelerated 8-to-16 bit bridging which boosted firmware throughput so that a low-end 8-bit 8051 core sufficed. Wrote APB, I2C, SPI and UART device drivers in Keil AX51 Assembly & C51 'C'
- Integrated DDR2/3-SDRAM-controller soft and mixed-signal-PHY hard IP in a TSMC 90nm test chip, using COT flow. Created comprehensive requirements specs for IP vendors and coordinated their deliverables. Wrote DC synthesis and PTSI sign-off scripts in TCL & SDC and guided P&R towards timing closure. Worked with Product and Test Engineering to characterize the IP, then assisted the (AXI-based) SoC to integrate it
- Led prototyping of MoCA modem, which included MAC with QAM2to256 data pump in a Virtex4 LX200 FPGA baseband board and OFDM RF stage built from discrete parts on a separate board. Designed on-chip PowerPC 405 embedded subsystem with DMA-enabled packet buffering. PPC ran the MAC layer (soft, in firmware) and DSP coefficient management. Worked very closely with firmware and DSP system engineers
- Facilitated Simulink acceleration of a DFE/FFE CDR algorithm using a Virtex5 SXT50 FPGA (Xilinx ML506 board with System Generator & AccelDSP platform). Facilitated emulation of a Fractional PLL algorithm in FPGA
- Used Synopsys DC Ultra, VCS, Prime Time SI, Formality; Mentor Precision RTL, QuestaSim with SV/SVA and OVM; Cadence Incisive/NC-Log; SpringSoft Verdi. Worked with users of Cadence Virtuoso & Magma flows
> Received performance-based awards
(Public Company; CMTN; Telecommunications industry)
October 2000 — June 2006 (5 years 9 months)
(Public Company; NT; Telecommunications industry)
July 1997 — September 2000 (3 years 3 months)
(Privately Held; Telecommunications industry)
September 1993 — June 1997 (3 years 10 months)
(Public Company; Industrial Automation industry)
May 1989 — March 1993 (3 years 11 months)
BSEE , Control Theory & Electronics , 1984 — 1989
With honors.
Endorsed by:
- US Department of Labor
- University of Toronto, Canada
Food/spices/BBQ * Learning & Discovery * Handyman * Gardening * Publishing * Music * History
OpenCores member (http://www.opencores.org)
- Achievement Award, 2008
- Leader of the Pack Award, 2004
- Graduation Honors, 1989
- Student of Generation Award, 1980-84 class
- Silver Medal in State Contest in Physics, 1983
- Gold Medal in State Contest in Latin, 1982