William Hung

Senior Staff R&D Engineer / Senior R&D Manager at Synopsys

San Francisco Bay Area

Current
  • Vice Chair, Quantum Computing Task Force at IEEE Computational Intelligence Society
  • Senior Staff R&D Engineer / Senior R&D Manager at Synopsys
Past
Education
  • Portland State University
  • The University of Texas at Austin
  • The University of Texas at Austin
Connections
212 connections
Industry
Semiconductors
Websites

William Hung’s Summary

R&D professional with broad experience in Electronic Design Automation, CPU Design and Verification.

Published over 40 refereed papers in various IEEE/ACM journals and conferences.

Also participated in several professional organizations, and served as:

Publications Chair, Formal Methods in Computer Aided Design (FMCAD), 2009;
Special Session Chair, IEEE World Congress on Computational Intelligence (WCCI), 2008;
Session Chair, ACM/IEEE Design Automation Conference (DAC) 2006;
Program Committee, IEEE/ACM Design Automation and Test in Europe (DATE) 2005, 2006, 2008, 2009, and 2010;
Program Committee, IEEE Congress on Evolutionary Computation (CEC) 2006, 2007 and 2008;
Program Committee, IEEE International Computer Software and Applications Conference (COMPSAC) 2005;
IEEE CIS Emergent Technologies Technical Committee 2004.

William Hung’s Specialties:

FPGA Synthesis, Physical Design, Formal Verification, Simulation and Emulation, Dynamic Verification, VLSI CAD, Logic Synthesis


William Hung’s Experience

  • Vice Chair, Quantum Computing Task Force

    IEEE Computational Intelligence Society

    (Educational Institution; 5001-10,000 employees; Non-Profit Organization Management industry)

    April 2008Present (1 year 9 months)

    Vice Chair, Quantum Computing Task Force
    Emergent Technologies Technical Committee
    IEEE Computational Intelligence Society

  • Senior Staff R&D Engineer / Senior R&D Manager

    Synopsys

    (Public Company; SNPS; Computer Software industry)

    November 2007Present (2 years 2 months)

    Electronic Design Automation

  • Senior Staff Engineer / Director

    Synplicity

    (Public Company; 201-500 employees; SYNP; Semiconductors industry)

    September 2004November 2007 (3 years 3 months)

    EDA (Electronic Design Automation) development

  • Senior Component Design Engineer

    Intel

    (Public Company; 10,001 or more employees; INTC; Semiconductors industry)

    June 1997August 2004 (7 years 3 months)

    Formal Methods for Microprocessor Design and Verification

  • Internship

    National Instruments

    (Public Company; 1001-5000 employees; NATI; Computer Hardware industry)

    July 1996August 1996 (2 months)

    Internship on ASIC design and verification


William Hung’s Education

  • Portland State University

    PhD , Electrical and Computer Engineering , 19992002

    Over 30 publications in various journals and conferences.

    For example:

    W.N.N.Hung et al, "Optimal Synthesis of Multiple Output Boolean Functions using a Set of Quantum Gates by Symbolic Reachability Analysis", IEEE Trans. CAD, 25(9), 2006.

    G.Yang, W.N.N.Hung et al, "Majority-Based Reversible Logic Gates", Theoretical Computer Science, 334(1-3), 2005.

    W.N.N.Hung et al, "Routability Checking for Three-Dimensional Architectures", IEEE Trans. VLSI, 12(12), 2004.

    L.Cheng, W.N.N.Hung et al, "Congestion Estimation for 3D Circuit Architectures", IEEE Trans. Circuits and Systems II, 51(12), 2004.

    W.N.N.Hung et al, "Segmented Channel Routability via Satisfiability", ACM Trans. Design Automation of Electronic Systems, 9(4), 2004.

    X.Song, W.N.N.Hung et al., "Board-level Multi-Terminal Net Assignment for the Partial Crossbar Architecture", IEEE Trans. VLSI, 11(3), 2003.

    W.N.N.Hung et al, "BDD Minimization by Scatter Search", IEEE Trans. CAD, 21(8), 2002.

    ......

  • The University of Texas at Austin

    MS , Electrical and Computer Engineering , 19961997

  • The University of Texas at Austin

    BS , Electrical and Computer Engineering , 19911994

    Activities and Societies:
    Tau Beta Pi, Eta Kappa Nu, Golden Key National Honor Society, IEEE, ACM

Additional Information

William Hung’s Websites:

William Hung’s Interests:

Reconfigurable Computing, Quantum Computing, Nanotechnology

William Hung’s Groups:

  •    Texas Exes/University of Texas at Austin
  •    The Official IEEE Group
  •    Semiconductor Professional's Group
  •    Intel Alumni Association
  •    Intel Alumni Network
  •    ASIC & FPGA Engineers: www.ASICForum.com
  •    FPGA - Field Programmable Gate Array
  •    FPGA/CPLD Design Group
  •    IEEE Computational Intelligence Society
  •    synopsys employees & alumni
  •    Design Verification Professionals
  •    Synplicity
  •    Formal Methods: Specification, Verification, TCG
  •    Quantum Information Science
  •    Synopsys

William Hung’s Honors:

IEEE Senior Member, since April 2008;
Intel Quality Award, 2003;
Outstanding Ph.D., ECE Dept, Portland State University, 2002;
Engineering Scholar, The University of Texas at Austin, 1993-1994;
Dean's Honor Roll, The University of Texas at Austin, 1992-1994.


William Hung’s Contact Settings

Interested In:

  • career opportunities
  • new ventures
  • expertise requests
  • business deals
  • reference requests
  • getting back in touch

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