Diarmuid Collins

Past

• IC Design Engineer (Silicon & Software Systems Contractor) at Texas Instruments (TI)
• IC Design Engineer at Silicon & Software Systems (S3)
• IC Design Engineer at Silicon & Software Systems (S3)

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Recommended

4 people have recommended Diarmuid

Connections

196 connections

Industry

Semiconductors

Diarmuid Collins’s Summary

Diarmuid Collins’s Specialties:

synthesis, front end design, environment/flow creation, perl scripting, STA, module design and specification, verification, gate level simulations

Diarmuid Collins’s Experience

• IC Design Engineer (Silicon & Software Systems Contractor)

  Texas Instruments (TI)

  (Public Company; 10,001 or more employees; TXN; Semiconductors industry)

  October 2003 — May 2008 (4 years 8 months)

  OCP Interconnect Module Flow Development
  
  • Developed design and verification flow for OCP Interconnect modules in OMAP based designs
  • Complete flow from RTL generation to module release created in perl. Steps include: RTL generation using Sonics/Arteris tools; synthesis script generation; synthesis using Synopsys Design Compiler; formal verification using Cadence Lec; status reporting to webpage and numerous other steps..
  • Designs generated by flow used successfully in working silicon on a number of generations of OMAP chips, including OMAP 2430C, 3430, 1035 and Wrigley3G.
  
  
  OMAP4 Firewall Design
  
  • Implemented design of OCP Interconnect firewall to be used in OMAP4 based designs.
  • Perl generator implemented to create Verilog RTL
  
  
  OMAP 1035 L3 & L4 Interconnect Delivery
  
  • Responsible for specification and release of the Sonics SMX and s3220 based OCP Interconnect modules in OMAP 1035 Ecosto. (5 modules)

• IC Design Engineer

  Silicon & Software Systems (S3)

  (Privately Held; 201-500 employees; Semiconductors industry)

  October 2002 — September 2003 (1 year)

  960k Megacell migration to 90nm design
  Synthesis using Synopsys Design Compile
  Formal Verificaiton using Formality
  STA using Primetime

• IC Design Engineer

  Silicon & Software Systems (S3)

  (Privately Held; 201-500 employees; Semiconductors industry)

  September 1997 — November 2001 (4 years 3 months)

  Microprocessor interface spec and design in VHDL.
  Automatic rtl generation (vhdl) of register map using perl
  Formal Verification using Chrysalis
  Timing Analysis using Primetime
  Testbench design using VHDL
  Function and TDL vector generation and simulation using IKOS
  Gate Level simulations on SONET switch