
Software Engineer at Consentry Networks
San Francisco Bay Area

Software Engineer at Consentry Networks
San Francisco Bay Area
Prior experience as an ASIC designer, now working as a software engineer. I tend to focus on platform and systems programming, at relatively low levels like kernel subsystems and device drivers.
ASIC and system bringup
(Privately Held; 51-200 employees; Computer & Network Security industry)
August 2005 — Present (3 years 4 months)
Software support for a massively multithreaded network processor to implement identity-aware network security policies.
(Public Company; 501-1000 employees; EXTR; Computer Networking industry)
August 2002 — August 2005 (3 years 1 month)
Provided extensive software input into next generation Extreme switch ASICS, from feature set definition down to optimization of register access.
Developed tools to instrument and analyze software performance, uncovering several significant bottlenecks in common operations.
One of the primary resources for Linux/MIPS work, including debugging issues in VM and interrupt handling and filesystems implementation.
Defined and implemented the underlying software control mechanism for a large chassis switch product, a framework to maintain distributed state.
(Privately Held; 1-10 employees; Computer Networking industry)
December 2000 — February 2002 (1 year 3 months)
Defined system architecture and began implementation of next generation of access networking using Ethernet in the First Mile. System included extensive IP and QoS features. Hardware architecture relied on FPGAs and switch fabrics for quick time to market. Software architecture used an embedded Linux kernel with remote administration of all services.
Extensive contributions to the IEEE 802.3ah standards working group.
(Public Company; 10,001 or more employees; SUNW; Computer Hardware industry)
August 1992 — December 2000 (8 years 5 months)
From August 1997 - December 2000: Senior Staff Engineer
Architectural role for several network interfaces for Sun Solaris platforms, including gigabit ethernet and OC-48 Packet over Sonet. Designs included significant packet processing and TCP/IP acceleration features. Emphasis was on total system performance, achieved by tailoring the NIC design to the needs of the rest of the system.
From Feb 1996 - August 1997: Staff Engineer (SW)
Implemented Solaris kernel driver for SBus and PCI OC-12 ATM interface. Implemented test programs and software workarounds of hardware bugs.
From June 1992 - Feb 1996: Member of Technical Staff (ASIC)
Designed the receive segmentation and reassembly core and DMA engine
for an OC-12 ATM interface for Sun workstations, using Verilog HDL and Synopsys toolset. Involved in all phases of the design from early brainstorming through bench debug and bringup. Extensive involvement in software interface and TCP/IP protocol acceleration issues.
MS, Computer Science, 1992 — 1997
BS, Electrical Engineering, 1988 — 1992
22 granted US patents