Chaitanya Polapragada

Chaitanya Polapragada

Design Verification at Apple

Location
San Francisco Bay Area
Industry
Semiconductors

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Chaitanya Polapragada's Overview

Current
  • Design Verification at Apple
Past
Education
Connections

286 connections

Websites

Chaitanya Polapragada's Summary

Goals:
Gain strong knowledge in the design verification of SOC's, building on my strong foundation in the areas of logic design, functional verification and signal processing.

Experience:
5 years of work experience in the design verification of SPARC server processor SOC's and HDD/SSD storage controllers. In addition, 3 years of academic experience specializing in digital design and telecommunication.

• Functional verification of L3 Cache on next-gen SPARC processors
• Verifciation of High-speed Hard-disk and Flash-drive controllers, helping build FPGA prototypes, design coverage measurement and improvement techniques using C, C++, verilog and Synopsys tools (Present)
• Practical code designs for video transmission over relay channels using state of the art LDPC and other error correction techniques using C++
• Design/Verification of high speed UART's in a voice control processor using python serial port library
• GUI based RFID system for a cadet's inventory using VB.Net

Specialties

Digital Design Verification of L3 cache, Hard-Disk and Flash Drive Controllers, Error Control Codes, Video Compression and Transmission techniques & Digital Signal Processing.


TECHNICAL SKILLS:

Languages: SystemVerilog, Verilog, C, C++, Perl, Assembly
Tools & Methodologies: VMM, VCS & Virsim, Design Compiler

Chaitanya Polapragada's Experience

Design Verification

Apple

November 2012Present (1 year 11 months) San Francisco Bay Area

Hardware Engineer

Oracle Corporation

Public Company; 10,001+ employees; ORCL; Information Technology and Services industry

September 2010November 2012 (2 years 3 months)

Functional verification of Coherency subsystem for next generation volume servers

Senior Engineer

Link-A-Media Devices

Public Company; 51-200 employees; Semiconductors industry

February 2008September 2010 (2 years 8 months)

Digital Design Verification of HDD and SSD Controller SOC's

Graduate Research Student, Multimedia Lab

Texas A&M University

Educational Institution; 10,001+ employees; Higher Education industry

May 2006December 2008 (2 years 8 months)

Code designs for video transmission over relay channels.

Graduate Assistant

Texas A&M University

Educational Institution; 10,001+ employees; Higher Education industry

20072008 (1 year)

Intern-Digital Design & Validation

Zarlink Semiconductor

Public Company; 1001-5000 employees; ZL; Semiconductors industry

20072007 (less than a year)

Design/Verification of Voice Control Processor ASIC.

Chaitanya Polapragada's Skills & Expertise

  1. Verilog
  2. SystemVerilog
  3. C++
  4. C
  5. VMM
  6. Perl
  7. Processors

Chaitanya Polapragada's Education

Texas A&M University

Master of Science, Electrical Engineering

20052008

Activities and Societies: Graduate Research Student-Multimedia Lab, Graduate Assistant-Industrial Distribution Dept., IEEE student member.

National Institute of Technology Warangal

Bachelor of Technology, Electronics and Communication Engineering

20012005

Activities and Societies: Event Co-ordinator- All-India Technical Symposium SANKET'04, Executive Member-Literary and Debating Club, Event Coordinator- All-India Cultural Festival, NITW'01.

Sri Chaitanya

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