
EDA Languages and Synthesis Tools Developer, PhD, at Synopsys
San Francisco Bay Area

EDA Languages and Synthesis Tools Developer, PhD, at Synopsys
San Francisco Bay Area
(Public Company; 1001-5000 employees; SNPS; Computer Software industry)
2002 — Present (7 years )
(Public Company; 1001-5000 employees; CDNS; Computer Software industry)
1999 — 2002 (3 years )
Place-and-route: Floorplan rule checking; buffer insertion on global nets.
Ph.D. , Computer Science
IEEE Working Group Chairman's Award for contribution to the IEEE Std. 1800-2005 "SystemVerilog" standard.