Brian Pharris

Past

• VLSI Design Engineer at Stream Processors, Inc
• Hardware Engineer at NVIDIA
• Research Assistant at MIT Lab of Computer Science

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Education

• Massachusetts Institute of Technology

Recommended

1 person has recommended Brian

Connections

132 connections

Industry

Computer Hardware

Brian Pharris’s Summary

Talented and versatile digital ASIC design engineer with recognized ability to ramp up quickly and contribute significantly to project success. Experience in full life cycle of ASIC development, including architectural and micro-architectural specification, RTL design, synthesis and static timing analysis, verification, emulation, and bring-up.

Brian Pharris’s Specialties:

Proficient in Verilog (including VPI, PLI), SystemVerilog, C++, C, Perl, and Python.
Experience with VCS, PrimeTime, Design Compiler, Formality, FormalPro.
Interconnect standards including PCI Express, USB, OCP, AXI, and AHB.
Excellent written and verbal communication skills.

Brian Pharris’s Experience

• VLSI Design Engineer

  Stream Processors, Inc

  (Privately Held; Semiconductors industry)

  April 2007 — September 2009 (2 years 6 months)

  * Design and RTL (verilog) implementation of a number of components, including a microprocessor, a stream processor load-store unit, and various SoC interconnect bridges and components.
  * Integration, verification and debug of third-party IP for USB and PCI Express
  * FPGA design prototyping, debug, and test harness development
  * Developed core elements of verification infrastructure. Significantly improved verification productivity by developing a Python-C++-VPI integration layer for use in RTL simulations.
  * Designed and implemented a unified test environment for use in simulation, emulation, and bring-up

• Hardware Engineer

  NVIDIA

  (Public Company; NVDA; Computer Hardware industry)

  July 2004 — April 2007 (2 years 10 months)

  * Architectural specification and modeling, micro-architecture design, and RTL implementation for cryptography and high-performance data transfer blocks.
  * Developed multiple verification environments, including a constraint solver, unit test benches, system-level test benches, and bus functional models.
  * Static timing analysis and optimization
  * Successfully performed a number of short-term assignments to accelerate schedule-critical project elements.

• Research Assistant

  MIT Lab of Computer Science

  (Research industry)

  September 2002 — May 2004 (1 year 9 months)

  * Designed and implemented an FPGA-based processor testing and energy characterization platform
  * Developed high-performance, energy-aware DRAM controller for SCALE-0 processor
  * Wrote performance-accurate C++ model of SCALE memory system

Brian Pharris’s Education

• Massachusetts Institute of Technology

  MEng, BS , Electrical Engineering and Computer Science , 1997 — 2004

  Concentration in Computer Systems and Architecture