Andrew Farris

Current

• Research Scientist at Lockheed Martin Aeronautics

Past

• Graduate Student at Cal Poly State University
• Applications Engineer Intern at Henkel Corporation
• Web Applications Programmer at MediaStorm.la

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Education

• California Polytechnic State University-San Luis Obispo
• California Polytechnic State University-San Luis Obispo

Connections

21 connections

Industry

Defense & Space

Websites

• My Website
• Published Research

Andrew Farris’s Summary

Electronics and computer engineer, antenna design, digital design, VLSI, embedded systems, computer architecture design and simulation, digital signal processing, software.

Andrew Farris’s Specialties:

Experienced with powerful industry tools, (FEKO, HFSS, SPICE, Cadence Allegro, Electric, Matlab, Minitab, Office), digital logic design approaches and tradeoffs, programming, low-level debugging and scripting in a variety of languages (C/C++, Java, assembly, Fortran, bash, PHP, Python, and MySQL). Web application developer. Linux tools development, systems administration, open-source community interaction, UI debugging and bug reporting, user support and training.

Andrew Farris’s Experience

• Research Scientist

  Lockheed Martin Aeronautics

  (Public Company; LMT; Defense & Space industry)

  January 2009 — Present (7 months)

  Electromagnetics Division

• Graduate Student

  Cal Poly State University

  (Educational Institution; 1001-5000 employees; Higher Education industry)

  September 2006 — June 2008 (1 year 10 months)

  Graduate study in Electrical Engineering, research in electronics drop impact reliability

• Applications Engineer Intern

  Henkel Corporation

  (Public Company; Electrical/Electronic Manufacturing industry)

  July 2007 — September 2007 (3 months)

  Lead-free solder reliability research done in partnership between Henkel and Cal Poly.

• Web Applications Programmer

  MediaStorm.la

  (Internet industry)

  December 2003 — May 2007 (3 years 6 months)

  Developed website back-ends for MySQL database, xhtml and xml data, debugging
  Secure handling of sensitive user data, financial transaction processing, forms processing

Andrew Farris’s Education

• California Polytechnic State University-San Luis Obispo

  Masters , Electrical Engineering , 2006 — 2008

  Graduate study in Electrical Engineering. Focus of study in the areas of digital design, embedded systems, and computer architecture. Thesis research work in lead-free solder reliability, drop impact testing, high-speed data acquisition systems, board-level electronics failure analysis, underfill application for drop impact reliability.

  Activities and Societies:

  IEEE, IMAPS, SMTA, Cal Poly Linux Users Group (CPLUG), member of student chapters

• California Polytechnic State University-San Luis Obispo

  Bachelor of Science , Computer Engineering , 2002 — 2006

  Worked on a portion of the Cal Poly CiNIC advanced integrated smart network card project, testing an embedded system incorporating multiple FPGAs and hardware interfaces.

  Activities and Societies:

  IEEE, IMAPS, SMTA, Cal Poly Linux Users Group (CPLUG), member of student chapters

Additional Information

Andrew Farris’s Websites:

• My Website
• Published Research

Andrew Farris’s Interests:

Digital Design, VLSI, Mixed Signal and RF Circuits, Programmable Logic, Computer Architecture, Hardware, Mobile and Low Power Computing, Linux, Embedded Systems, Electromagnetic Radiation, Antennas, and Communications Hardware

Andrew Farris’s Groups:

IEEE, IMAPS, SMTA, Cal Poly Linux Users Group (CPLUG)

•    The Official IEEE Group
•    California Polytechnic State University Alumni
•    Cal Poly Alumni SLO
•    California Polytechnic University San Luis Obispo Alumni
•    Cal Poly Alumni Association
•    Southern California Electronics

Andrew Farris’s Honors:

Received grant from the San Jose Chapter of SMTA in 2008 for lasting contribution to drop impact reliability of lead-free solder and chip scale packages.

Publications:
A. Farris, J. Pan, A. Liddicoat, B. J. Toleno, D. Maslyk, D. Shangguan, J. Bath, D. Willie, D. A. Geiger, “Drop test reliability of lead-free chip scale packages”, Proc. of 2008 IEEE ECTC, pp. 1173-1180.

M. Krist, J. Pan, A. Farris, N. Vickers, “Drop impact dynamic response study of JEDEC JESD22-B111 test board”, Proceedings of the 41th International Symposium on Microelectronics (IMAPS’2008), Providence, RI, USA, Nov. 1 – 6, 2008.

N. Vickers, K. Rauen, A. Farris, J. Pan, “Board Level Failure Analysis of Chip Scale Package Drop Test Assemblies”, Proceedings of the 41th International Symposium on Microelectronics (IMAPS’2008), Providence, RI, USA, Nov. 1 – 6, 2008.

Andrew Farris’s Contact Settings

Interested In:

• career opportunities
• new ventures
• reference requests
• getting back in touch