
Research Scientist at Lockheed Martin Aeronautics
Greater Los Angeles Area

Research Scientist at Lockheed Martin Aeronautics
Greater Los Angeles Area
Electronics and computer engineer, antenna design, digital design, VLSI, embedded systems, computer architecture design and simulation, digital signal processing, software.
Experienced with powerful industry tools, (FEKO, HFSS, CST Studio, Catia 5, SPICE, Cadence Allegro, Matlab, Minitab, Electric, MS Office, Visual Studio), digital logic design approaches and tradeoffs, programming, low-level debugging and scripting, multiple languages (C/C++, Java, assembly, Fortran, bash, PHP, Python, and MySQL). Web application developer. Linux tools, systems administration, open-source community interaction, UI debugging, bug reporting, user support and training.
(Public Company; LMT; Defense & Space industry)
January 2009 — Present (11 months)
ADP Electromagnetics Division, Skunk Works
(Educational Institution; 1001-5000 employees; Higher Education industry)
September 2006 — June 2008 (1 year 10 months)
Graduate study in Electrical Engineering, research in electronics drop impact reliability
(Public Company; Consumer Goods industry)
July 2007 — September 2007 (3 months)
Lead-free solder reliability research done in partnership between Henkel Electronics, Flextronics International, and Cal Poly SLO.
(Internet industry)
December 2003 — May 2007 (3 years 6 months)
Developed website back-ends for MySQL database, xhtml and xml data, debugging
Secure handling of sensitive user data, financial transaction processing, forms processing
Masters , Electrical Engineering , 2006 — 2008
Graduate study in Electrical Engineering. Focus of study in the areas of digital design, embedded systems, and computer architecture. Thesis research work in lead-free solder reliability, drop impact testing, high-speed data acquisition systems, board-level electronics failure analysis, underfill application for drop impact reliability.
Bachelor of Science , Computer Engineering , 2002 — 2006
Worked on a portion of the Cal Poly CiNIC advanced integrated smart network card project, testing an embedded system incorporating multiple FPGAs and hardware interfaces.
Digital Design, VLSI, Mixed Signal and RF Circuits, Programmable Logic, Computer Architecture, Hardware, Mobile and Low Power Computing, Linux, Embedded Systems, Electromagnetic Radiation, Antennas, and Communications Hardware
IEEE, IMAPS, SMTA, Cal Poly Linux Users Group (CPLUG)
Received grant from the San Jose Chapter of SMTA in 2008 for lasting contribution to drop impact reliability of lead-free solder and chip scale packages.
Publications:
"Drop Impact Reliability of Edge-bonded Lead-free Chip Scale Packages", Microelectronics Reliability, Vol. 49, No. 7, 2009, pp. 761-770.
“Drop test reliability of lead-free chip scale packages”, Proc. of 2008 IEEE ECTC, pp. 1173-1180.
“Drop impact dynamic response study of JEDEC JESD22-B111 test board”, Proceedings of the 41th International Symposium on Microelectronics (IMAPS’2008), Providence, RI, USA, Nov. 1 – 6, 2008.
“Board Level Failure Analysis of Chip Scale Package Drop Test Assemblies”, Proceedings of the 41th International Symposium on Microelectronics (IMAPS’2008), Providence, RI, USA, Nov. 1 – 6, 2008.