Alexander Smirnov

Current

• QofR SW Engineer at Mentor Graphics
• PhD student at Boston University

Past

• Technical intern at Synopsys
• Researcher, software engineer at Universitat Polytecnica de Catalunya
• Software engineer at Reksoft

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Education

• Boston University
• Sankt-Peterburgskij Gosudarstvennyj Elektrotehniceskij Universitet 'LETI'

Connections

109 connections

Industry

Computer Software

Websites

• My Website

Alexander Smirnov’s Summary

Graduating 1/2009 with Ph.D. from ECE, Boston University. Experienced in asynchronous circuits synthesis, formal verification and currently working in a high-level synthesis (HLS) group.

Alexander Smirnov’s Specialties:

Asynchronous circuits, EDA, synthesis, formal verification. Synopsys ASIC design flow, Cadence back-end, Xilinx FPGA design flow, formal methods. Languages: C++, VHDL, Verilog, TCL, UML/OOT, sh, Perl, .NET...

Alexander Smirnov’s Experience

• QofR SW Engineer

  Mentor Graphics

  (Public Company; 1001-5000 employees; MENT; Computer Software industry)

  June 2008 — Present (1 year 6 months)

• PhD student

  Boston University

  (Educational Institution; 5001-10,000 employees; Research industry)

  September 2002 — Present (7 years 3 months)

  PhD candidate since De. 2005 at the ECE department. Conduct research in the area of asynchronous micropipeline synthesis. Support my research by development of Weaver – EDA flow for asynchronous micropipeline synthesis from synthesizable HDL specifications.

• Technical intern

  Synopsys

  (Public Company; SNPS; Computer Software industry)

  May 2007 — August 2007 (4 months)

  R&D in the area of formal verification within Synopsys ATG.

• Researcher, software engineer

  Universitat Polytecnica de Catalunya

  (Public Company; 5001-10,000 employees; Higher Education industry)

  February 2000 — July 2002 (2 years 6 months)

  Worked at the LSI (ECE) department on the following.
  Evaluating alternative verification strategies in the framework of TranSyT – formal verification tool for complex timed circuits.
  Part-time developing TaxoSynthesis speed-independent circuits’ synthesis tool.
  Developing libraries for the Metropolis co-design tool.

• Software engineer

  Reksoft

  (Privately Held; 51-200 employees; Computer Software industry)

  September 1997 — February 2000 (2 years 6 months)

  Developing software for GSM network operators from requirements negotiation and specification, architecture design and approval to release support and change requests implementation.
  Managed one of such projects.

Alexander Smirnov’s Education

• Boston University

  Ph.D. , Electrical and Computer Engineering , 2002 — 2008

  Concentrated on asynchronous circuits synthesis from conventional synthesizable HDL specification. The goal is achieved by using existing synthesis engine for initial synthesis and reimplementing the "synchronous" netlist into asynchronous micropipeline using the specified asynchronous library.

• Sankt-Peterburgskij Gosudarstvennyj Elektrotehniceskij Universitet 'LETI'

  Systems Engineer , Automation and Control Systems , 1989 — 1995

Additional Information

Alexander Smirnov’s Websites:

• My Website

Alexander Smirnov’s Interests:

Electronic Design Automation, high-level synthesis, asynchronous circuits synthesis verification test and application, high-level system specification formalisms, timed systems verification, Petri nets, STG, unfoldings

Alexander Smirnov’s Groups:

•    Boston University Engineering Graduate School Alumni

Alexander Smirnov’s Contact Settings

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