Ausaaf Khan

Current

• Hardware Engineer at Intel

Past

• Hardware Engineer at NVIDIA
• Logic Design Engineer at Intel
• ASIC Design Engineer at Texas Instruments

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Education

• The University of Texas at Austin
• Georgia Institute of Technology
• Oklahoma State University

• Sharjah College
• Al Ma'Arifa International High School, Sharjah
• Cambridge High School, Dubai
• St Rosary School, Sharjah

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4 more...

Connections

80 connections

Industry

Semiconductors

Ausaaf Khan’s Summary

Computer Engineer with broad experience in ASIC and Microprocessor design. Experienced in logic design using Verilog HDL and schematic entry tools. Solid background in physical design. Proficient in the use of PERL and unix scripting to automate design and pre-silicon verification tasks and methodologies. Hands on experience working on the Memory Execution Unit on x86 micro processors.

Ausaaf Khan’s Specialties:

Microprocessor Design;
ASIC(Application Specific Integrated Circuit) Design;
Logic/Phyiscal Design;
Verilog HDL Design;
Schematic Design using Candence Opus.
Memory Execution Unit design for x86 processors.
PERL and Unix scripting.

Ausaaf Khan’s Experience

• Hardware Engineer

  Intel

  (Public Company; INTC; Semiconductors industry)

  June 2007 — Present (2 years 2 months)

  Memory Execution Unit Design.

• Hardware Engineer

  NVIDIA

  (Public Company; 1001-5000 employees; NVDA; Computer Hardware industry)

  April 2005 — March 2007 (2 years)

  •Involved in all aspects of ASIC design. Primary responsibilites include system and unit level verification on nFORCE series of integrated chipsets for AMD platforms

• Logic Design Engineer

  Intel

  (Public Company; 10,001 or more employees; INTC; Computer Hardware industry)

  February 2001 — March 2005 (4 years 2 months)

  • Designed, implemented and verified different blocks within the ReOrder Buffer unit in the Sequencer Cluster on TEJAS, a 4GHz Intel Pentium 4 design.
  Responsibilities included gate level design of functional verilog, timing closure and full chip integration using top down physical data provided by the physical design cluster.
  Major tasks included resolution of critical paths, fub level lef/def consolidation, Noise and ERC/RV certification, level 1 functional debug, FEV, Perl scripting and CVS file management.
  • Participated in establishing a semi-custom design flow using standard cells and manual placement directives.
  The flow was used in the design of the entire Floating Point Unit and several data path intensive units including the event and exception handler.
  This resulted in significant reduction in schedule, overall cost and risks through the elimination of expensive mask design effort and re spin.

• ASIC Design Engineer

  Texas Instruments

  (Public Company; 10,001 or more employees; TXN; Semiconductors industry)

  February 1998 — January 2001 (3 years)

  • Modification and design reuse of TI and third party IP cores for use in turn key System on Chip designs. Worked on I2C master, slave modules, bus functional models for system verification, IEEE 1394 link layer controller modules for data transmission framing

Ausaaf Khan’s Education

• The University of Texas at Austin

  MSEE , Computer Engineering , 2009

• Georgia Institute of Technology

  MSEE , Computer Engineering , 2000 — 2000

  completed 9 hours of course work beforing transfering to UT Austin.

• Oklahoma State University

  BSEE , Electrical Engineering , 1994 — 1997

• Sharjah College

  1993 — 1994

• Al Ma'Arifa International High School, Sharjah

  1991 — 1993

• Cambridge High School, Dubai

  1986 — 1991

• St Rosary School, Sharjah

  1981 — 1986