Lead ASIC Design Engineer at Open-Silicon
India
- Current
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- Lead ASIC Design Engineer at Open-Silicon
- Education
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- University of Michigan
- Connections
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111
connections
- Industry
- Semiconductors
- Websites
Aditya Ramachandran’s Summary
Lead ASIC Design Engineer building robust ASIC methodologies and innovative ASIC technologies that add value in terms of intellectual property and technological differentiation. Interested in EDA technology and advanced ASIC methodologies.
Aditya Ramachandran’s Specialties:
ASIC technology, ASIC methodology, Design-for-test (DFT) , Low-Power Design, ASIC/ EDA workflow automation
Aditya Ramachandran’s Experience
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Lead ASIC Design Engineer
Open-Silicon
(Semiconductors industry)
July 2003 — Present (6 years 5 months)
- Develop new ASIC technologies not addressed by existing tools and implement by re-using existing EDA infrastructure or, if required, complete ground-up implementation.
- Develop, implement and validate robust ASIC methodologies ( 45nm design, 65nm design, 90nm design, low-power design)
- Develop automated EDA workflow environments ( Specification, implementation, validation, design team training and support)
- Evaluate EDA tools and features
Aditya Ramachandran’s Education
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University of Michigan
MSEE , Signal Processing , 2001 — 2003
- Research Assistant, Department of Radiology (Medical Imaging)
- Detection and 3D Imaging of Tumors in Ultrasound Image Sets
- GUI Development
- Image Processing Algorithm Development
- Active Contour Algorithms in C++
Additional Information
Aditya Ramachandran’s Websites:
Aditya Ramachandran’s Honors:
- Best Paper Award, SNUG Bangalore (2008)
- Open-Silicon President's Award (2007)
- Best Paper Award, SNUG Bangalore (2007)
- Open-Silicon SPOTLIGHT Award (2004, 2006)
- Open-Silicon Achievement Award (2005)
Aditya Ramachandran’s Contact Settings
Interested In:
- career opportunities
- consulting offers
- new ventures
- job inquiries
- expertise requests
- business deals
- reference requests
- getting back in touch
