Semiconductor Manufacturing

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Mohammad Oves

We're experiencing problem with wafer overlay due to grid distortion on a particular product/flow. Rest of the products belong to this technology don't show this problem. Suggestions?

Yield Engineer, Advanced Technology Group at Maxim Integrated

  • Comment (9)
  • August 1, 2012
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Comments

  • James C.

    James

    James C.

    Semiconductor Manufacturing Process Tech. & Business OP Professional

    You may like to check if the alignment marks quality has compromised after a particular process step.

  • Rene G.

    Rene

    Rene G.

    Photolithography Development Engineer

    I agree with James - check waveforms of the fine alignment marks on the scanner/stepper to be sure you have strong signals. It is possible that alignment marks have been damaged due to over/under-etching, etc. Is this device/step being exposed on only one stepper/scanner or multiple stepper/scanners? If so, then is this problem occurring on all of them or only one? If only on one, then maybe lens matching could be an action you could have your equipment engineering group do before you go further....?

  • John B.

    John

    John B.

    Quality Engineering Manager at International Rectifier

    Is the distortion at reticle field level or across wafer? Is this error associated with a particular product or process flow that only this product uses?

  • Yehiel G.

    Yehiel

    Yehiel G.

    Looking for opportunities. Consulting OK.

    It is sometimes related to a significantly different pattern density for a particular product, which develops a significantly different wafer stress (and distortion) on pre-litho operations (dep or etch). Even CMP on will perform differently if the wafer stress is significantly different after the pre-CMP deposition step

  • John B.

    John

    John B.

    Quality Engineering Manager at International Rectifier

    Two possible sources of error, wafer warp or target distortion. Both can be influenced by pattern density and layout. Isolate the first layer you start to see grid distortion and look for process non-uniformity (for example a thermal gradient across the wafer to compensate for non-uniform film deposition) this particular layout may be more impacted. Also, if you use wafer level alignment targets optimize the dummy fill pattern around the target to minimize CMP/process target distortion.

  • Dave S.

    Dave

    Dave S.

    Operations Manager for Adecco assigned: Google

    Check Die to Die on two failed wafers to see if the distortion is absoultely repeatable

  • Greg G.

    Greg

    Greg G.

    Department Manager Thin Films & CMP at Spansion

    1. Is it real? xSEM or xTEM to verify that the misalignment you think you are experiencing is real.
    2. Try different marks. The marks in silicon 1st layer or earliest layer you can repeatably align to are good candidates.
    3. Change mark location to other candidates on the wafer or add more alignment targets to your job. You'll pay a throughput hit, but might get acceptable registration.
    4. Run a DOE on prior CMP layer to see if over/under polish is inadvertantly changing your alignment mark.
    5. Is one RTA tool corrupting your marks?

    I've dealt with all of the above examples.

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